SLASF30 January   2022 TAA5212

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Serial Interfaces
        1. 8.3.2.1 Control Serial Interfaces
        2. 8.3.2.2 Audio Serial Interfaces
          1. 8.3.2.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.2.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.2.2.3 Left-Justified (LJ) Interface
        3. 8.3.2.3 Using Multiple Devices With Shared Buses
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Programmable Microphone Bias
      7. 8.3.7 Signal-Chain Processing
        1. 8.3.7.1 ADC Signal-Chain
          1. 8.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 8.3.7.1.2 Programmable Channel Gain Calibration
          3. 8.3.7.1.3 Programmable Channel Phase Calibration
          4. 8.3.7.1.4 Programmable Digital High-Pass Filter
          5. 8.3.7.1.5 Programmable Digital Biquad Filters
          6. 8.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 8.3.7.1.7 Configurable Digital Decimation Filters
            1. 8.3.7.1.7.1 Linear Phase Filters
              1. 8.3.7.1.7.1.1 Sampling Rate: 16 kHz or 14.7 kHz
              2. 8.3.7.1.7.1.2 Sampling Rate: 24 kHz or 22.05 kHz
              3. 8.3.7.1.7.1.3 Sampling Rate: 32 kHz or 29.4 kHz
              4. 8.3.7.1.7.1.4 Sampling Rate: 48 kHz or 44.1 kHz
              5. 8.3.7.1.7.1.5 Sampling Rate: 96 kHz or 88.2 kHz
      8. 8.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 8.3.9 Programmable Channel Phase Calibration
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 VEGA Registers
      2. 8.5.2 TAA5212 Registers
      3. 8.5.3 TAA5212 Registers
    6. 8.6 Feature Description
    7. 8.7 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM target mode and PLL on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC PERFORMANCE FOR INPUT RECORDING
Differential input full-scale AC signal voltage AC-coupled input 2 VRMS
Differential input full-scale AC signal voltage DC-coupled input 4 VRMS
Single-ended input full-scale AC signal voltage AC-coupled input 1 VRMS
Single-ended input full-scale AC signal voltage DC-coupled input 2 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 118 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) IN1 differential AC-coupled input selected and AC signal shorted to ground, 12-dB channel gain 103 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) IN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain, Device in Hign Common Mode Tolerance Mode (ADC_CH1_CM_TOL and ADC_CH2_CM_TOL=2'b10) 110 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) IN1 differential DC-coupled input selected and AC signal shorted to ground, 12-dB channel gain, Device in Hign Common Mode Tolerance Mode (ADC_CH1_CM_TOL and ADC_CH2_CM_TOL=2'b10) 98 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) Wideband Mode: IN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain (Integrated till 20KHz A-Weighted) dB
SNR Signal-to-noise ratio(1)(2) Wideband Mode: IN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain (Integrated till 100KHz) 91 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) Power Tune Mode: IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 106 dB
Power Tune Mode: IN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 106
Power Tune Mode: IN1 differential DC-coupled input selected and AC signal shorted to ground, 12-dB channel gain 94
SNR Signal-to-noise ratio, A-weighted(1)(2) 1.8V AVDD Operation:IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 110 dB
1.8V AVDD Operation:IN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 104
SNR Signal-to-noise ratio, A-weighted(1)(2) 1.8V AVDD Operation:IN1 differential DC-coupled input selected and AC signal shorted to ground, 12-dB channel gain 92 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) 1.8V AVDD Operation + Power Tune Mode: IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 104 dB
1.8V AVDD Operation + Power Tune Mode: IN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 100
1.8V AVDD Operation + Power Tune Mode: IN1 differential DC-coupled input selected and AC signal shorted to ground, 12-dB channel gain 88
DR Dynamic range, A-weighted(2) IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 118 dB
IN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 110
DR Dynamic range, A-weighted(2) IN1 differential DC-coupled input selected and –72-dB full-scale AC signal input, 12-dB channel gain 98 dB
DR Dynamic range, A-weighted(2) Power Tune Mode: IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 106 dB
Power Tune Mode: IN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 106
Power Tune Mode: IN1 differential DC-coupled input selected and –72-dB full-scale AC signal input, 12-dB channel gain 94
DR Dynamic range, A-weighted(2) 1.8V AVDD Operation: IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 106 110 dB
1.8V AVDD Operation: IN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 104
DR Dynamic range, A-weighted(2) 1.8V AVDD Operation: IN1 differential DC-coupled input selected and –72-dB full-scale AC signal input, 12-dB channel gain 92 dB
DR Dynamic range, A-weighted(2) 1.8V AVDD Operation + Power Tune Mode: IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 104 dB
1.8V AVDD Operation + Power Tune Mode: IN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 100
1.8V AVDD Operation + Power Tune Mode: IN1 differential DC-coupled input selected and –72-dB full-scale AC signal input, 12-dB channel gain 88
THD+N Total harmonic distortion(2) IN1 differential AC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –95 TBD dB
IN1 differential DC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –95
THD+N Total harmonic distortion(2) IN1 differential DC-coupled input selected and –13-dB full-scale AC signal input, 12-dB channel gain –91 dB
ADC OTHER PARAMETERS
Input impedance Differential input, between INxP and INxM, 5kΩ Mode 5.5 kΩ
Input impedance Differential input, between INxP and INxM, 10kΩ Mode 11 kΩ
Input impedance Differential input, between INxP and INxM, 40kΩ Mode 44 kΩ
Input impedance Single-ended input, between INxP and INxM, 5kΩ Mode 2.75 kΩ
Input impedance Single-ended input, between INxP and INxM,10kΩ Mode 5.5 kΩ
Input impedance Single-ended input, between INxP and INxM, 40kΩ Mode 22 kΩ
Offset Shorted Input. TBD mV
Digital volume control range Programmable 0.5-dB steps –80 47 dB
Input Signal Bandwidth Upto 192KSPS FS Rate 0.46 FS
>192KSPS 90 kHz
Output data sample rate Programmable 3.675 768 kHz
Output data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3-dB point (default setting)		 2 Hz
Interchannel isolation –1-dB full-scale AC signal line-in input to non measurement channel –134 dB
Interchannel gain mismatch –6-dB full-scale AC signal line-in input, 0-dB channel gain 0.1 dB
Interchannel phase mismatch 1-kHz sinusoidal signal 0.01 Degrees
PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 92 dB
CMRR Common-mode rejection ratio Differential microphone input selected, 0-dB channel gain, 1-VRMS AC input, 1-kHz signal on both pins and measure level at output, ADC_CHx_CFG0 D3-2 register bits set to 2b'10 to configure device in high CMRR performance mode 80 dB
MICROPHONE BIAS
MICBIAS noise BW = 20 Hz to 20 kHz, A-weighted, 1-µF capacitor between MICBIAS and AVSS 2 µVRMS
MICBIAS voltage Bypass to AVDD AVDD V
MICBIAS voltage AVDD=1.8V 1.375 V
MICBIAS voltage AVDD=3.3V 2.75 V
DIGITAL I/O
VIL(SHDNZ) Low-level digital input logic voltage threshold SHDNZ pin –0.3 0.25 × IOVDD V
VIH(SHDNZ) High-level digital input logic voltage threshold SHDNZ pin 0.75 × IOVDD IOVDD + 0.3 V
VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8-V operation –0.3 0.35 × IOVDD V
All digital pins except SDA and SCL, IOVDD 3.3-V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8-V operation 0.65 × IOVDD IOVDD + 0.3 V
All digital pins except SDA and SCL, IOVDD 3.3-V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V
All digital pins except SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation 0.4
VOH High-level digital output voltage All digital pins except SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V
All digital pins except SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation 2.4
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 × IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 × IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3 mA, IOVDD > 2 V 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus 20
IIL Input logic-low leakage for digital inputs All digital pins, input = 0 V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode (software shutdown mode) All device external clocks stopped TBD µA
IIOVDD 1
IAVDD Current consumption when MICBIAS ON, MICBIAS voltage 10 V, 30 mA load, ADC off fS = 48 kHz, BCLK = 256 × fS TBD mA
IIOVDD 0.01
IAVDD Current consumption with ADC 2-channel operation at fS 16-kHz, MICBIAS off, PLL on, BCLK = 512 × fS TBD mA
IIOVDD 0.1
IAVDD Current consumption with ADC 2-channel operation at fS 48-kHz, MICBIAS on, PLL off, BCLK = 512 × fS TBD mA
IIOVDD 0.1
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.