SLASF29A January   2022  – October 2024 TAA5242

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Analog Input Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Integrated Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 Configurable Digital Decimation Filters
          1. 6.3.7.1.1 Linear-phase filters
            1. 6.3.7.1.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.7.1.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.7.1.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.7.1.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.7.1.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.7.1.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.7.1.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.7.1.2 Low-latency Filters
            1. 6.3.7.1.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 6.3.7.1.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 6.3.7.1.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 6.3.7.1.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 6.3.7.1.2.5 Sampling Rate: 192kHz or 176.4kHz
        2. 6.3.7.2 Programmable Digital High-Pass Filter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.4 Analog Input Configurations

The device supports simultaneous recording of up to two channels using the high-performance stereo ADC. The device consists of two pairs of analog input pins (INxP and INxM) which can be configured in single-ended or differential input mode by setting MD4 and MD5 pins. The input source for the analog pins can be from electret-condenser analog microphones, micro electrical-mechanical system (MEMS) analog microphones, or line-in (auxiliary) inputs from the system board.

The voice or audio signal inputs can be capacitively coupled (AC-coupled) or DC-coupled to the device. For best distortion performance, use of low-voltage coefficient capacitors for AC-coupling is recommended. The typical input impedance for the TAA5242 is 5 kΩ for the INxP or INxM pins with ±20% variation. The value of the coupling capacitor in AC-coupled mode must be chosen so that the high-pass filter formed by the coupling capacitor and the input impedance do not affect the signal content. Before proper recording can begin, this coupling capacitor must be charged up to the common-mode voltage at power-up. To enable quick charging, the device has a quick charge scheme to speed up the charging of the coupling capacitor at power-up when operating in I2S/LJ target mode. This input cap quick charge setting can be enabled by configuring the MD3 pin. The MD3 pin also configures the digital HPF cut-off frequency when the device is operating in I2S/LJ target mode.

For optimal performance, the common-mode variation at the device input should be limited to less than 100mVpp for AC-coupled settings. For applications that cannot avoid large common-mode fluctuations, the device offers the modes to configure the device for higher common-mode tolerance. Table 6-11 shows the analog input configuration modes available with MD4 and MD5 configuration.

Table 6-10 Input Cap Quick-Charge and HPF Selection in Target I2S/LJ Mode
MD3 INPUT CAP QUICK CHARGE HPF CUT-OFF FREQUENCY
Low Disabled 1Hz @ 48kHz sampling rate
High Enabled 12Hz @ 48kHz sampling rate
Table 6-11 Analog Input Configurations
MD5 MD4 ANALOG INPUT CONFIGURATION
Low Low Differential input; AC-Coupled only
Low High Differential input; AC or DC-Coupled with High Common Mode Tolerance
High Low Single-Ended input on INxP; AC-Coupled only
High High Single-Ended input on INxP; AC or DC-Coupled with High Common Mode Tolerance

Figure 6-8 to Figure 6-11 show the typical configuration diagrams for the various input configuration modes.

TAA5242 DC-Coupled Microphone or Line Differential Input Connection Figure 6-8 DC-Coupled Microphone or Line Differential Input Connection
TAA5242 DC-Coupled Microphone or Line Single-Ended Input Connection Figure 6-9 DC-Coupled Microphone or Line Single-Ended Input Connection
TAA5242 AC-Coupled Microphone or Line Differential Input Connection Figure 6-10 AC-Coupled Microphone or Line Differential Input Connection
TAA5242 AC-Coupled Microphone or Line Single-Ended Input Connection Figure 6-11 AC-Coupled Microphone or Line Single-Ended Input Connection

The device also supports channel select configurations to enable mono or stereo input in I2S and LJ Modes. This can be configured by setting MD6 pin. Table 6-12 shows the control for this feature with MD6 configuration. ADC Channel-2 is disabled when MD6 pin is set to High. In TDM mode, MD6 pin function is as described in Figure 6-2.

Table 6-12 Input Channel Select configuration in I2S and LJ Modes
MD6 ANALOG INPUT CONFIGURATION
Low Stereo ADC
High Mono 1-Channel ADC (IN1x enabled, IN2x disabled)