SLASFC3 January 2024 TAC5111-Q1
ADVANCE INFORMATION
The device playback channel includes a high dynamic range, built-in digital interpolation filter to process the input data stream to generate digital data stream for multibit delta-sigma (ΔΣ) modulator. The interpolation filter can be chosen from four different types, depending on the required frequency response, group delay, power consumption, and phase linearity requirements for the target application. The selection of the interpolation filter option can be done by configuring the DAC_DSP_INTX_FILT, P0_R115_D[7:6] register bits. Low power filter can be configured by setting DAC_LOW_PWR_FILT, P0_R79_D2 bit. Table 7-33 shows the configuration register setting for the decimation filter mode selection for the record channel.
P0_R79_D2 : DAC_LOW_PWR_FILT | P0_R115_D[7:6] : DAC_DSP_INTX_FILT[1:0] | INTERPOLATION FILTER MODE SELECTION |
---|---|---|
0 | 00 (default) | Linear phase filters are used for the interpolation |
0 | 01 | Low latency filters are used for the interpolation |
0 | 10 | Ultra-low latency filters are used for the interpolation |
0 | 11 | Reserved (do not use this setting) |
1 | x | Low power filters are used for the interpolation |