SLASFC3 January   2024 TAC5111-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 6.14 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Input Channel Configurations
      4. 7.3.4 Output Channel Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Programmable Microphone Bias
      7. 7.3.7 Signal-Chain Processing
        1. 7.3.7.1 ADC Signal-Chain
          1. 7.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.1.2 Programmable Channel Gain Calibration
          3. 7.3.7.1.3 Programmable Channel Phase Calibration
          4. 7.3.7.1.4 Programmable Digital High-Pass Filter
          5. 7.3.7.1.5 Programmable Digital Biquad Filters
          6. 7.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 7.3.7.1.7 Configurable Digital Decimation Filters
            1. 7.3.7.1.7.1 Linear Phase Filters
              1. 7.3.7.1.7.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 7.3.7.1.7.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 7.3.7.1.7.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 7.3.7.1.7.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 7.3.7.1.7.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 7.3.7.1.7.1.6 Sampling Rate: 384kHz or 352.8kHz
        2. 7.3.7.2 DAC Signal-Chain
          1. 7.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.2.2 Programmable Channel Gain Calibration
          3. 7.3.7.2.3 Programmable Digital High-Pass Filter
          4. 7.3.7.2.4 Programmable Digital Biquad Filters
          5. 7.3.7.2.5 Programmable Digital Mixer
          6. 7.3.7.2.6 Configurable Digital Interpolation Filters
            1. 7.3.7.2.6.1 Linear Phase Filters
              1. 7.3.7.2.6.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 7.3.7.2.6.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 7.3.7.2.6.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 7.3.7.2.6.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 7.3.7.2.6.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 7.3.7.2.6.1.6 Sampling Rate: 384kHz or 352.8kHz
      8. 7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
  9. 8 Register Maps
    1. 8.1 TAC5212 Registers
    2. 8.2 TAC5212 Registers
    3. 8.3 TAC5212 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2 TAC5212 Registers

Table 8-108 lists the memory-mapped registers for the TAC5212 registers. All register offset addresses not listed in Table 8-108 should be considered as reserved locations and the register contents should not be modified.

Table 8-108 TAC5212 Registers
AddressAcronymRegister NameReset ValueSection
0x0PAGE_CFGDevice page register0x00PAGE_CFG Register (Address = 0x0) [Reset = 0x00]
0x3DSP_CFG00x00DSP_CFG0 Register (Address = 0x3) [Reset = 0x00]
0xDCLK_CFG00x00CLK_CFG0 Register (Address = 0xD) [Reset = 0x00]
0xECHANNEL_CFG10x00CHANNEL_CFG1 Register (Address = 0xE) [Reset = 0x00]
0xFCHANNEL_CFG20x00CHANNEL_CFG2 Register (Address = 0xF) [Reset = 0x00]
0x17SRC_CFG0SRC configuration register 10x00SRC_CFG0 Register (Address = 0x17) [Reset = 0x00]
0x18SRC_CFG1SRC configuration register 20x00SRC_CFG1 Register (Address = 0x18) [Reset = 0x00]
0x19JACK_DET_CFG0JACK DET configuration register 00x00JACK_DET_CFG0 Register (Address = 0x19) [Reset = 0x00]
0x1AJACK_DET_CFG1JACK DET configuration register 10x00JACK_DET_CFG1 Register (Address = 0x1A) [Reset = 0x00]
0x1BJACK_DET_CFG2JACK DET configuration register 20x00JACK_DET_CFG2 Register (Address = 0x1B) [Reset = 0x00]
0x1CJACK_DET_CFG3JACK DET configuration register 30x00JACK_DET_CFG3 Register (Address = 0x1C) [Reset = 0x00]
0x1ELPAD_CFG1LPAD0x20LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]
0x1FLPSG_CFG1LPSG0x80LPSG_CFG1 Register (Address = 0x1F) [Reset = 0x80]
0x20LPAD_LPSG_CFG1LPAD and LPSG common configuration register 10x00LPAD_LPSG_CFG1 Register (Address = 0x20) [Reset = 0x00]
0x23LIMITER_CFGLimiter configuration register 20x00LIMITER_CFG Register (Address = 0x23) [Reset = 0x00]
0x24AGC_DRC_CFGAGC_DRC configuration register 20x00AGC_DRC_CFG Register (Address = 0x24) [Reset = 0x00]
0x2BPLIM_CFG0PLIM configuration register 00x00PLIM_CFG0 Register (Address = 0x2B) [Reset = 0x00]
0x2CMIXER_CFG0MISC configuration register 00x00MIXER_CFG0 Register (Address = 0x2C) [Reset = 0x00]
0x2DMISC_CFG0MISC configuration register 00x00MISC_CFG0 Register (Address = 0x2D) [Reset = 0x00]
0x2EBRWNOUT0xBFBRWNOUT Register (Address = 0x2E) [Reset = 0xBF]
0x2FINT_MASK0Interrupt Mask Register-00xFFINT_MASK0 Register (Address = 0x2F) [Reset = 0xFF]
0x32INT_MASK4Interrupt Mask Register-30x00INT_MASK4 Register (Address = 0x32) [Reset = 0x00]
0x33INT_MASK5Interrupt Mask Register-30x30INT_MASK5 Register (Address = 0x33) [Reset = 0x30]
0x34INT_LTCH0Latched Interrupt Readback Register-00x00INT_LTCH0 Register (Address = 0x34) [Reset = 0x00]
0x35CHx_LTCHSummary of Diagnostics0x00CHx_LTCH Register (Address = 0x35) [Reset = 0x00]
0x38OUT_CH1_LTCH0x00OUT_CH1_LTCH Register (Address = 0x38) [Reset = 0x00]
0x39OUT_CH2_LTCH0x00OUT_CH2_LTCH Register (Address = 0x39) [Reset = 0x00]
0x3AINT_LTCH1Latched Interrupt Readback Register-00x00INT_LTCH1 Register (Address = 0x3A) [Reset = 0x00]
0x3BINT_LTCH2Latched Interrupt Readback Register-30x00INT_LTCH2 Register (Address = 0x3B) [Reset = 0x00]
0x3CINT_LIVE0Live Interrupt Readback Register-00x00INT_LIVE0 Register (Address = 0x3C) [Reset = 0x00]
0x3DCHx_LIVESummary of Diagnostics0x00CHx_LIVE Register (Address = 0x3D) [Reset = 0x00]
0x40OUT_CH1_LIVE0x00OUT_CH1_LIVE Register (Address = 0x40) [Reset = 0x00]
0x41OUT_CH2_LIVE0x00OUT_CH2_LIVE Register (Address = 0x41) [Reset = 0x00]
0x42INT_LIVE1Latched Interrupt Readback Register-00x00INT_LIVE1 Register (Address = 0x42) [Reset = 0x00]
0x43INT_LIVE2Latched Interrupt Readback Register-30x00INT_LIVE2 Register (Address = 0x43) [Reset = 0x00]
0x4EDIAG_CFG80xBADIAG_CFG8 Register (Address = 0x4E) [Reset = 0xBA]
0x4FDIAG_CFG90x4BDIAG_CFG9 Register (Address = 0x4F) [Reset = 0x4B]
0x54DIAG_CFG140x48DIAG_CFG14 Register (Address = 0x54) [Reset = 0x48]
0x55DIAGDATA_CFG0x00DIAGDATA_CFG Register (Address = 0x55) [Reset = 0x00]
0x58DIAG_MON_MSB_MBIAS0x00DIAG_MON_MSB_MBIAS Register (Address = 0x58) [Reset = 0x00]
0x59DIAG_MON_LSB_MBIAS0x01DIAG_MON_LSB_MBIAS Register (Address = 0x59) [Reset = 0x01]
0x62DIAG_MON_MSB_OUT1P0x00DIAG_MON_MSB_OUT1P Register (Address = 0x62) [Reset = 0x00]
0x63DIAG_MON_LSB_OUT1P0x06DIAG_MON_LSB_OUT1P Register (Address = 0x63) [Reset = 0x06]
0x64DIAG_MON_MSB_OUT1M0x00DIAG_MON_MSB_OUT1M Register (Address = 0x64) [Reset = 0x00]
0x65DIAG_MON_LSB_OUT1M0x07DIAG_MON_LSB_OUT1M Register (Address = 0x65) [Reset = 0x07]
0x66DIAG_MON_MSB_OUT2P0x00DIAG_MON_MSB_OUT2P Register (Address = 0x66) [Reset = 0x00]
0x67DIAG_MON_LSB_OUT2P0x08DIAG_MON_LSB_OUT2P Register (Address = 0x67) [Reset = 0x08]
0x68DIAG_MON_MSB_OUT2M0x00DIAG_MON_MSB_OUT2M Register (Address = 0x68) [Reset = 0x00]
0x69DIAG_MON_LSB_OUT2M0x09DIAG_MON_LSB_OUT2M Register (Address = 0x69) [Reset = 0x09]
0x6ADIAG_MON_MSB_TEMP0x00DIAG_MON_MSB_TEMP Register (Address = 0x6A) [Reset = 0x00]
0x6BDIAG_MON_LSB_TEMP0x0ADIAG_MON_LSB_TEMP Register (Address = 0x6B) [Reset = 0x0A]
0x6CDIAG_MON_MSB_MBIAS_LOAD0x00DIAG_MON_MSB_MBIAS_LOAD Register (Address = 0x6C) [Reset = 0x00]
0x6DDIAG_MON_LSB_MBIAS_LOAD0x0BDIAG_MON_LSB_MBIAS_LOAD Register (Address = 0x6D) [Reset = 0x0B]
0x6EDIAG_MON_MSB_AVDD0x00DIAG_MON_MSB_AVDD Register (Address = 0x6E) [Reset = 0x00]
0x6FDIAG_MON_LSB_AVDD0x0CDIAG_MON_LSB_AVDD Register (Address = 0x6F) [Reset = 0x0C]
0x70DIAG_MON_MSB_GPA0x00DIAG_MON_MSB_GPA Register (Address = 0x70) [Reset = 0x00]
0x71DIAG_MON_LSB_GPA0x0DDIAG_MON_LSB_GPA Register (Address = 0x71) [Reset = 0x0D]

8.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 8-109.

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The device memory map is divided into pages. This register sets the page.

Table 8-109 PAGE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W00000000bThese bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255

8.2.2 DSP_CFG0 Register (Address = 0x3) [Reset = 0x00]

DSP_CFG0 is shown in Table 8-110.

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Table 8-110 DSP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6RESERVEDR/W0bReserved bit; Write only reset value
5RESERVEDR/W0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR/W0bReserved bit; Write only reset value
2RESERVEDR/W0bReserved bit; Write only reset value
1DIS_DVOL_OTF_CHGR/W0bDisable run-time changes to DVOL settings.
0d = Digital volume control changes supported while ADC is powered-on
1d = Digital volume control changes not supported while ADC is powered-on.
0EN_BQ_OTF_CHGR/W0bEnable run-time changes to Biquad settings.
0d = Disable on the fly biquad changes
1d = Enable on the fly biquad changes

8.2.3 CLK_CFG0 Register (Address = 0xD) [Reset = 0x00]

CLK_CFG0 is shown in Table 8-111.

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Table 8-111 CLK_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7CNT_TGT_CFG_OVR_PASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per PASI_CNT_CFG bit.
1d = Override the standard behavior of the PASI_CNT_CFG. In this case the clock auto detect feature is not available.
PASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
PASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
6CNT_TGT_CFG_OVR_SASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per SASI_CNT_CFG bit.
1d = Override the standard behavior of the SASI_CNT_CFG. In this case the clock auto detect feature is not available.
SASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
SASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
5RESERVEDR0bReserved bit; Write only reset value
4-3RESERVEDR/W00bReserved bits; Write only reset values
2PASI_USE_INT_FSYNCR/W0bFor Primary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
1SASI_USE_INT_FSYNCR/W0bFor Secondary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
0RESERVEDR/W0bReserved bit; Write only reset value

8.2.4 CHANNEL_CFG1 Register (Address = 0xE) [Reset = 0x00]

CHANNEL_CFG1 is shown in Table 8-112.

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Table 8-112 CHANNEL_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7FORCE_DYN_MODE_CUST_MAX_CHR/W0bADC Force dynamic mode custom max channel
0d = In Dynamicmode , Max channel is based on ADC_DYN_MAXCH_SEL
1d = In Dynamic mode, max channel is custom as DYN_MODE_CUST_MAX_CH
6-3DYN_MODE_CUST_MAX_CH[3:0]R/W0000bADC Dynamic mode custom max channel configuration
[3]->CH4_EN
[2]->CH3_EN
[1]->CH2_EN
[0]->CH1_EN
2-0RESERVEDR000bReserved bits; Write only reset values

8.2.5 CHANNEL_CFG2 Register (Address = 0xF) [Reset = 0x00]

CHANNEL_CFG2 is shown in Table 8-113.

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Table 8-113 CHANNEL_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7DAC_FORCE_DYN_MODE_CUST_MAX_CHR/W0bDAC Force dynamic mode custom max channel
0d = In Dynamic, Max channel is based on DAC_DYN_MAXCH_SEL
1d = In Dynamic mode, max channel is custom as per DAC_DYN_MODE_CUST_MAX_CH
6-3DAC_DYN_MODE_CUST_MAX_CH[3:0]R/W0000bDAC Dynamic mode custom max channel configuration ([3]->CH4_EN, [2]->CH3_EN, [1]->CH2_EN, [0]->CH1_EN)
[3]->CH4_EN
[2]->CH3_EN
[1]->CH2_EN
[0]->CH1_EN
2-0RESERVEDR000bReserved bits; Write only reset values

8.2.6 SRC_CFG0 Register (Address = 0x17) [Reset = 0x00]

SRC_CFG0 is shown in Table 8-114.

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This register is configuration register 1 for SRC.

Table 8-114 SRC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7SRC_ENR/W0bSRC enable config
0b = SRC disable
1b = SRC enable
6DIS_AUTO_SRC_DETR/W0bSRC auto detect config
0b = SRC auto detect enabled
1b = SRC auto detect disabled
5-0RESERVEDR000000bReserved bits; Write only reset value

8.2.7 SRC_CFG1 Register (Address = 0x18) [Reset = 0x00]

SRC_CFG1 is shown in Table 8-115.

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This register is configuration register 2 for SRC.

Table 8-115 SRC_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7MAIN_FS_CUSTOM_CFGR/W0bMain Fs custom config
0b = Main Fs is auto inferred
1b = Main Fs need to be selected from MAIN_FS_SELECT_CFG
6MAIN_FS_SELECT_CFGR/W0bMain Fs select config
0b = PASI Fs shall be used as Main Fs
1b = SASI Fs shall be used as Main Fs
5-3MAIN_AUX_RATIO_M_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = m is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved
2-0MAIN_AUX_RATIO_N_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = n is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved

8.2.8 JACK_DET_CFG0 Register (Address = 0x19) [Reset = 0x00]

JACK_DET_CFG0 is shown in Table 8-116.

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This register is the JACK DET configuration register 0.

Table 8-116 JACK_DET_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6JACK_DET_MONITOR_FREQ[1:0]R/W00bHeadset Detection Pulse Frequency
0d = 0.5 Hz
1d = 1 Hz
2d = 7.5 Hz
3d = 15 Hz
5JACK_DET_PULSE_WIDTHR/W0bDetector Pulse High Width
0d = 4ms (MICBIAS PIN Cap = 1 uF)
1d = 32ms (MICBIAS PIN Cap = 10 uF)
4RESERVEDR/W0bReserved bit; Write only reset value
3RESERVEDR/W0bReserved bit; Write only reset value
2-1HPDET_CLOCK_SEL[1:0]R/W00bHeadphone Detection Clock Timeperiod Select
0d = 1ms
1d = 2ms
2d = 4ms
3d = Reserved
0RESERVEDR/W0bReserved bit; Write only reset value

8.2.9 JACK_DET_CFG1 Register (Address = 0x1A) [Reset = 0x00]

JACK_DET_CFG1 is shown in Table 8-117.

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This register is the JACK DET configuration register 1.

Table 8-117 JACK_DET_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6JACK_DET_COMP_CTRL2R/W0bHook Press Threshold Control in Fixed External Resistance case, controls the choice of Lowest Microphone impedance to be supported or Highest Hook button Impedance to be supported
0d = Minimum Microphone resistance supported, R_Mic = 800 Ωs and Max Hook button impedance supported, R_Hook = 320 Ωs for AC coupled Headphones R26<3> = 0 (else, when R26<3> = 1, R_hook = 150 Ωs)
1d = Max Hook button impedance supported, R_hook = 680 Ωs and Minimum Microphone resistance supported, R_Mic = 1350 Ωs for AC coupled Headphones R26<3> = 0 (else, when R26<3> = 1, R_Mic = 1750 Ωs)
5-4JACK_DET_COMP_CTRL3[1:0]R/W00bHook Pressed Jack Insertion support, valid only for External Resistor Type P0_R25_D4 = 0 else Don't care.
0d = supports minimum Hook button impedance of 150 Ωs for Hook Pressed Jack Insertion detection
1d = supports minimum Hook button impedance of 100 Ωs for Hook Pressed Jack Insertion detection
2d = supports minimum Hook button impedance of 50 Ωs for Hook Pressed Jack Insertion detection
3d = Reserved
3HPDET_COUPLINGR/W0bHeadphone detect coupling
0d = AC coupled
1d = DC coupled
2HPDET_USE_2x_CURRR/W0bHeadset detect current sel config
0d = 2x current for headphone detection disabled
1d = 2x current for headphone detection enabled
1JACK_DET_ENR/W0bHeadset Detection Enable
0d = Headset Detection Disabled
1d = Headset Detection Enabled
0RESERVEDR0bReserved bit; Write only reset value

8.2.10 JACK_DET_CFG2 Register (Address = 0x1B) [Reset = 0x00]

JACK_DET_CFG2 is shown in Table 8-118.

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This register is the JACK DET configuration register 2.

Table 8-118 JACK_DET_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6HPDET_DEBR/W0bHeadphone Detection Debounce Programmability
0d = No Debounce
1d = Debounce of 3 detections
5-3JACK_DET_DEB_INSERT[2:0]R/W000bHeadset Insert Detection Debounce Programmability
0d = Debounce Time = 16ms
1d = Debounce Time = 32ms
2d = Debounce Time = 64ms
3d = Debounce Time = 128ms
4d = Debounce Time = 256ms
5d = Debounce Time = 512ms
6d = Reserved. Don not use
7d = No Debounce
2JACK_DET_DEB_REMOVALR/W0bHeadset Removal Detection Debounce Programmability
0d = Debounce of 5 detections
1d = Debounce of 3 detections
1-0JACK_DET_DEB_HOOK_PRESS[1:0]R/W00bHook Press Debounce config
0d = No Debounce
1d = No Debounce
2d = Debounce of 2 detections
3d = Debounce of 3 detections

8.2.11 JACK_DET_CFG3 Register (Address = 0x1C) [Reset = 0x00]

JACK_DET_CFG3 is shown in Table 8-119.

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This register is the JACK DET configuration register 3.

Table 8-119 JACK_DET_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-6JACK_TYPE_FLAG[1:0]R00bHeadset Jack type flag
0d = Jack is not inserted
1d = Jack is inserted without Microphone
2d = Reserved. Do not use
3d = Jack is inserted with Microphone
5-4HEADSET_TYPE_DET[1:0]R00bHeadset type
0d = Headset is not inserted
1d = Jack is inserted with mono-HS (RIGHT)
2d = Jack is inserted with mono-HS (LEFT)
3d = Jack is inserted with stereo-HS
3-0RESERVEDR0000bReserved bits; Write only reset value

8.2.12 LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]

LPAD_CFG1 is shown in Table 8-120.

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Low Power Activity Detection. Voice activity detection or Ultrasonic Activity detection configuration register 1

Table 8-120 LPAD_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPAD_MODE[1:0]R/W00bAuto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down
1d = VAD/UAD interrupt based ADC power up and ADC power down
2d = VAD/UAD interrupt based ADC power up but user initiated ADC power down
Dont use
5-4LPAD_CH_SEL[1:0]R/W10bVAD channel select.
0d = Channel 1 is monitored for VAD/UAD activity
1d = Channel 2 is monitored for VAD/UAD activity
2d = Channel 3 is monitored for VAD/UAD activity
3d = Channel 4 is monitored for VAD/UAD activity
3LPAD_SDOUT_INT_CFGR/W0bSDOUT interrupt configuration.
0d = SDOUT pin is not enabled for interrupt function
1d = SDOUT pin is enabled to support interrupt output when channel data in not being recorded
2RESERVEDR0bReserved bit; Write only reset value
1LPAD_PD_DET_ENR/W0bEnable ASI output data during VAD/UAD activity.
0d = VAD/UAD processing is not enabled during ADC recording
1d = VAD/UAD processing is enabled during ADC recording and VAD interrupts are generated as configured
0RESERVEDR/W0bReserved bit; Write only reset value

8.2.13 LPSG_CFG1 Register (Address = 0x1F) [Reset = 0x80]

LPSG_CFG1 is shown in Table 8-121.

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Low Power Signal Generation configuration register 1

Table 8-121 LPSG_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPSG_CH_SEL[1:0]R/W10bLPSG channel select.- UAG
0d = UAG activity is generated on channel 1
1d = UAG activity is generated on channel 2
2d = UAG activity is generated on channel 3
3d = UAG activity is generated on channel 4
5RESERVEDR/W0bReserved bit; Write only reset value
4-0RESERVEDR00000bReserved bits; Write only reset values

8.2.14 LPAD_LPSG_CFG1 Register (Address = 0x20) [Reset = 0x00]

LPAD_LPSG_CFG1 is shown in Table 8-122.

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This register is configuration register 1 for VAD/UAD/UAG.

Table 8-122 LPAD_LPSG_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPAD_LPSG_CLK_CFG[1:0]R/W00bClock select for VAD/UAD/UAG
0d = VAD/UAD/UAG processing using internal oscillator clock
1d = VAD/UAD/UAG processing using external clock on BCLK input
2d = VAD/UAD/UAG processing using external clock on CCLK input
3d = Custom clock configuration based on CNT_CFG, CLK_SRC and CLKGEN_CFG registers in page 0
5-4LPAD_LPSG_EXT_CLK_CFG[1:0]R/W00bClock configuration using external clock for VAD/UAD/UAG
0d = External clock is 24.576 MHz
1d = External clock is 6.144 MHz
2d = External clock is 12.288 MHz
3d = External clock is 18.432 MHz
3RESERVEDR/W0bReserved bit; Write only reset value
2LPAD_PH1_ENR/W0bEnable LPAD Phase 1 detection through Jack Detection comparator.
0d = LPAD phase 1 diabled
1d = LPAD phase 1 enabled
1-0RESERVEDR00bReserved bits; Write only reset values

8.2.15 LIMITER_CFG Register (Address = 0x23) [Reset = 0x00]

LIMITER_CFG is shown in Table 8-123.

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This register is configuration register 2 for Limiter.

Table 8-123 LIMITER_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6LIMITER_INP_SEL[1:0]R/W00bLimiter input select config
0d = max(dacin_ch0, dacin_ch1)
1d = dacin_ch1
2d = dacin_ch0
3d = avg(dacin_ch0, dacin_ch1)
5-4LIMITER_OUT_SEL[1:0]R/W00bLimiter output select config
0d = applied on both
1d = dacin_ch1
2d = dacin_ch0
3d = applied none
3-0RESERVEDR0000bReserved bits; Write only reset values

8.2.16 AGC_DRC_CFG Register (Address = 0x24) [Reset = 0x00]

AGC_DRC_CFG is shown in Table 8-124.

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This register is configuration register 2 for AGC_DRC.

Table 8-124 AGC_DRC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7AGC_CH1_ENR/W0bAGC Channel 1 enable config
0d = disable
1d = enable
6AGC_CH2_ENR/W0bAGC Channel 2 enable config
0d = disable
1d = enable
5AGC_CH3_ENR/W0bAGC Channel 3 enable config
0d = disable
1d = enable
4AGC_CH4_ENR/W0bAGC Channel 4 enable config
0d = disable
1d = enable
3DRC_CH1_ENR/W0bDRC Channel 1 enable config
0d = disable
1d = enable
2DRC_CH2_ENR/W0bDRC Channel 2 enable config
0d = disable
1d = enable
1DRC_CH3_ENR/W0bDRC Channel 3 enable config
0d = disable
1d = enable
0DRC_CH4_ENR/W0bDRC Channel 4 enable config
0d = disable
1d = enable

8.2.17 PLIM_CFG0 Register (Address = 0x2B) [Reset = 0x00]

PLIM_CFG0 is shown in Table 8-125.

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This register is configuration register 0 for PLIM.

Table 8-125 PLIM_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_PLIMR/W0bEnable PLIM
0d = Disable
1d = Enable
6-4PLIM_ATTN_VAL[2:0]R/W000bPLIM attenuation factor
0d = 0dB
1d = -6dB
2d = -12dB
3d = -18dB
4d = -24dB
5d = -30dB
6d = -36dB
7d = -42dB
3PLIM_BY_SAR_GPAR/W0bPLIM attenuation value source
0d = Plimit attentation based on GPIO and reg_plimi_attn_val
1d = Plimit attenuation based on GPA Analog voltage. LUT will map SAR ADC data to Attenuation factor
2PLIM_RECOVERYR/W0bPLIM attenuation recovery
0d = Plimit func doesn’t recover. It stays at same attenuation level or can apply more attenuation if required
1d = Plimit func recovers (reduces the attenuation) if “gpio_val=0” or “sar_adc_gpa” data suggest that Battery Voltage has recovered then we can reduce the attenuation being applied
1-0RESERVEDR00bReserved bits; Write only reset value

8.2.18 MIXER_CFG0 Register (Address = 0x2C) [Reset = 0x00]

MIXER_CFG0 is shown in Table 8-126.

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This register is the MISC configuration register 0.

Table 8-126 MIXER_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_DAC_ASI_MIXERR/W0bEnable DAC ASI Mixer
0b = Disabled
1b = Enabled
6EN_SIDE_CHAIN_MIXERR/W0bEnable Side Chain Mixer
0b = Disabled
1b = Enabled
5EN_ADC_CHANNEL_MIXERR/W0bEnable ADC Channel Mixer
0b = Disabled
1b = Enabled
4EN_LOOPBACK_MIXERR/W0bEnable Loopback Mixer
0b = Disabled
1b = Enabled
3-0RESERVEDR0000bReserved bits; Write only reset value

8.2.19 MISC_CFG0 Register (Address = 0x2D) [Reset = 0x00]

MISC_CFG0 is shown in Table 8-127.

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This register is the MISC configuration register 0.

Table 8-127 MISC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_DISTORTIONR/W0bDistortion Limiter enable config
0b = Distortion Limiter disable
1b = Distortion Limiter enable
6EN_BOPR/W0bBOP enable config
0b = BOP disable
1b = BOP enable
5EN_THERMAL_FOLDBACKR/W0bThermal Foldback enable config
0b = Thermal Foldback disable
1b = Thermal Foldback enable
4EN_DRCR/W0bDRC enable config
0b = DRC disable
1b = DRC enable
3DAC_SIGNAL_GENERATOR_1_ENABLER/W0bDAC signal generator 1 enable config
0b = Signal generator disabled
1b = Signal generator enabled
2DAC_SIGNAL_GENERATOR_2_ENABLER/W0bDAC signal generator 2 enable config
0b = Signal generator disabled
1b = Signal generator enabled
1DSP_VBAT_AVDD_SELR/W0bSAR data source select for DSP Limiter, BOP, DRC
0b = SAR VBAT data to DSP
1b = SAR AVDD data to DSP
0BRWNOUT_ENR/W0bBrownout enable config
0b = Brownout disable
1b = Brownout enable

8.2.20 BRWNOUT Register (Address = 0x2E) [Reset = 0xBF]

BRWNOUT is shown in Table 8-128.

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Table 8-128 BRWNOUT Register Field Descriptions
BitFieldTypeResetDescription
7-0BRWNOUT_THRS[7:0]R/W10111111bThreshold for brownout shutdown (IF P1_R45_D1->DSP_VBAT_AVDD_SEL=1)
Default = 7.8V (~2.7V)
Nd = ((0.9×(N*16)/4095)-0⋅211764)x17) (V) (((0.9×(N*16)/4095)-0⋅225)x6 (V))

8.2.21 INT_MASK0 Register (Address = 0x2F) [Reset = 0xFF]

INT_MASK0 is shown in Table 8-129.

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Interrupt masks.

Table 8-129 INT_MASK0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK0R/W1bClock error interrupt mask.
0b = Don't Mask
1b = Mask
6INT_MASK0R/W1bPLL Lock interrupt mask.
0b = Don't Mask
1b = Mask
5RESERVEDR/W1bReserved bit; Write only reset value
4RESERVEDR/W1bReserved bit; Write only reset value
3RESERVEDR/W1bReserved bit; Write only reset value
2RESERVEDR/W1bReserved bit; Write only reset value
1RESERVEDR/W1bReserved bit; Write only reset value
0RESERVEDR/W1bReserved bit; Write only reset value

8.2.22 INT_MASK4 Register (Address = 0x32) [Reset = 0x00]

INT_MASK4 is shown in Table 8-130.

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Interrupt masks.

Table 8-130 INT_MASK4 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6RESERVEDR/W0bReserved bit; Write only reset value
5INT_MASK4R/W0bOUT Short Circuit Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
4INT_MASK4R/W0bDRVR Virtual Ground Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
3INT_MASK4R/W0bHeadset insert detection interrupt mask.
0b = Don't Mask
1b = Mask
2INT_MASK4R/W0bHeadset remove detection interrupt mask.
0b = Don't Mask
1b = Mask
1INT_MASK4R/W0bHeadset detection hook(button) interrupt mask.
0b = Don't Mask
1b = Mask
0RESERVEDR/W0bReserved bit; Write only reset value

8.2.23 INT_MASK5 Register (Address = 0x33) [Reset = 0x30]

INT_MASK5 is shown in Table 8-131.

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Interrupt masks.

Table 8-131 INT_MASK5 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK5R/W0bGPA up threshold fault mask.
0b = Don't Mask
1b = Mask
6INT_MASK5R/W0bGPA low threshold fault mask.
0b = Don't Mask
1b = Mask
5INT_MASK5R/W1bVAD power up detect interrupt mask.
0b = Don't Mask
1b = Mask
4INT_MASK5R/W1bVAD power down detect interrupt mask.
0b = Don't Mask
1b = Mask
3RESERVEDR/W0bReserved bit; Write only reset value
2RESERVEDR/W0bReserved bit; Write only reset value
1RESERVEDR/W0bReserved bit; Write only reset value
0RESERVEDR/W0bReserved bit; Write only reset value

8.2.24 INT_LTCH0 Register (Address = 0x34) [Reset = 0x00]

INT_LTCH0 is shown in Table 8-132.

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Latched interrupt readback.

Table 8-132 INT_LTCH0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH0R0bInterrupt due to clock error (self clearing bit).
0b = No interrupt
1b = Interrupt
6INT_LTCH0R0bInterrupt due to PLL Lock (self clearing bit)
0b = No interrupt
1b = Interrupt
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.2.25 CHx_LTCH Register (Address = 0x35) [Reset = 0x00]

CHx_LTCH is shown in Table 8-133.

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Channel level Diagnostics Latched Status

Table 8-133 CHx_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7STS_CHx_LTCHR0bStatus of Input CH1_LTCH.
0b = No faults occurred in input channel 1
1b = Fault or Faults have occurred in input channel 1
6STS_CHx_LTCHR0bStatus of Input CH2_LTCH.
0b = No faults occurred in input channel 2
1b = Fault or Faults have occurred in input channel 2
5STS_CHx_LTCHR0bStatus of Output CH1_LTCH.
0b = No faults occurred in output channel 1
1b = Fault or Faults have occurred in output channel 1
4STS_CHx_LTCHR0bStatus of Output CH2_LTCH.
0b = No faults occurred in output channel 2
1b = Fault or Faults have occurred in output channel 2
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.2.26 OUT_CH1_LTCH Register (Address = 0x38) [Reset = 0x00]

OUT_CH1_LTCH is shown in Table 8-134.

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Table 8-134 OUT_CH1_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7OUT_CH1_LTCHR0bOUT1P Short Circuit Fault (self clearing bit).
0b = No short ciruit fault
1b = Short circuit fault
6OUT_CH1_LTCHR0bOUT1M Short Circuit Fault (self clearing bit).
0b = No short ciruit fault
1b = Short circuit fault
5OUT_CH1_LTCHR0bChannel 1 DRVRP Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault
1b = Virtual ground fault
4OUT_CH1_LTCHR0bChannel 1 DRVRM Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault
1b = Virtual ground fault
3MASK_ADC_CH1_OVRLD_FLAGR/W0bADC CH1 OVRLD fault mask.
0b = Don't Mask
1b = Mask
2MASK_ADC_CH2_OVRLD_FLAGR/W0bADC CH2 OVRLD fault mask.
0b = Don't Mask
1b = Mask
1-0RESERVEDR00bReserved bits; Write only reset value

8.2.27 OUT_CH2_LTCH Register (Address = 0x39) [Reset = 0x00]

OUT_CH2_LTCH is shown in Table 8-135.

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Table 8-135 OUT_CH2_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7OUT_CH2_LTCHR0bOUT2P Short Circuit Fault (self clearing bit).
0b = No short ciruit fault
1b = Short circuit fault
6OUT_CH2_LTCHR0bOUT2M Short Circuit Fault (self clearing bit).
0b = No short ciruit fault
1b = Short circuit fault
5OUT_CH2_LTCHR0bChannel 2 DRVRP Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault
1b = Virtual ground fault
4OUT_CH2_LTCHR0bChannel 2 DRVRM Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault
1b = Virtual ground fault
3-2RESERVEDR00bReserved bits; Write only reset value
1MASK_AREG_SC_FLAGR/W0bAREG SC fault mask.
0b = Don't Mask
1b = Mask
0AREG_SC_FLAG_LTCHR0bAREG SC fault (self clearing bit).
0b = No AREG short circuit fault
1b = AREG short ciruit fault

8.2.28 INT_LTCH1 Register (Address = 0x3A) [Reset = 0x00]

INT_LTCH1 is shown in Table 8-136.

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Latched interrupt readback.

Table 8-136 INT_LTCH1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3INT_LTCH1R0bInterrupt due to Headset Insert Detection (self clearing bit).
0b = No interrupt
1b = Interrupt
2INT_LTCH1R0bInterrupt due to Headset Remove Detection (self clearing bit).
0b = No interrupt
1b = Interrupt
1INT_LTCH1R0bInterrupt due to Headset hook(button) (self clearing bit).
0b = No interrupt
1b = Interrupt
0RESERVEDR0bReserved bit; Write only reset value

8.2.29 INT_LTCH2 Register (Address = 0x3B) [Reset = 0x00]

INT_LTCH2 is shown in Table 8-137.

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Latched interrupt readback.

Table 8-137 INT_LTCH2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH2R0bInterrupt due to GPA up threshold fault (self clearing bit).
0b = No interrupt
1b = Interrupt
6INT_LTCH2R0bInterrupt due to GPA low threshold fault (self clearing bit)
0b = No interrupt
1b = Interrupt
5INT_LTCH2R0bInterrupt due to VAD power up detect (self clearing bit).
0b = No interrupt
1b = Interrupt
4INT_LTCH2R0bInterrupt due to VAD power down detect (self clearing bit).
0b = No interrupt
1b = Interrupt
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.2.30 INT_LIVE0 Register (Address = 0x3C) [Reset = 0x00]

INT_LIVE0 is shown in Table 8-138.

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Latched interrupt readback.

Table 8-138 INT_LIVE0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE0R0bInterrupt due to clock error .
0b = No interrupt
1b = Interrupt
6INT_LIVE0R0bInterrupt due to PLL Lock
0b = No interrupt
1b = Interrupt
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.2.31 CHx_LIVE Register (Address = 0x3D) [Reset = 0x00]

CHx_LIVE is shown in Table 8-139.

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Channel level Diagnostics Live Status

Table 8-139 CHx_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7STS_CHx_LIVER0bStatus of Input CH1_LIVE.
0b = No faults occurred in input channel 1
1b = Fault or Faults have occurred in input channel 1
6STS_CHx_LIVER0bStatus of Input CH2_LIVE.
0b = No faults occurred in input channel 2
1b = Fault or Faults have occurred in input channel 2
5STS_CHx_LIVER0bStatus of Output CH1_LIVE.
0b = No faults occurred in output channel 1
1b = Fault or Faults have occurred in output channel 1
4STS_CHx_LIVER0bStatus of Output CH2_LIVE.
0b = No faults occurred in output channel 2
1b = Fault or Faults have occurred in output channel 2
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.2.32 OUT_CH1_LIVE Register (Address = 0x40) [Reset = 0x00]

OUT_CH1_LIVE is shown in Table 8-140.

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Table 8-140 OUT_CH1_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7OUT_CH1_LIVER0bOUT1P Short Circuit Fault .
0b = No short ciruit fault
1b = Short circuit fault
6OUT_CH1_LIVER0bOUT1M Short Circuit Fault .
0b = No short ciruit fault
1b = Short circuit fault
5OUT_CH1_LIVER0bChannel 1 DRVRP Virtual Ground Fault .
0b = No virtual ground fault
1b = Virtual ground fault
4OUT_CH1_LIVER0bChannel 1 DRVRM Virtual Ground Fault .
0b = No virtual ground fault
1b = Virtual ground fault
3-0RESERVEDR0000bReserved bits; Write only reset value

8.2.33 OUT_CH2_LIVE Register (Address = 0x41) [Reset = 0x00]

OUT_CH2_LIVE is shown in Table 8-141.

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Table 8-141 OUT_CH2_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7OUT_CH2_LIVER0bOUT2P Short Circuit Fault .
0b = No short ciruit fault
1b = Short circuit fault
6OUT_CH2_LIVER0bOUT2M Short Circuit Fault .
0b = No short ciruit fault
1b = Short circuit fault
5OUT_CH2_LIVER0bChannel 2 DRVRP Virtual Ground Fault .
0b = No virtual ground fault
1b = Virtual ground fault
4OUT_CH2_LIVER0bChannel 2 DRVRM Virtual Ground Fault .
0b = No virtual ground fault
1b = Virtual ground fault
3-1RESERVEDR000bReserved bits; Write only reset value
0AREG_SC_FLAG_LIVER0bAREG SC fault .
0b = No AREG short circuit fault
1b = AREG short ciruit fault

8.2.34 INT_LIVE1 Register (Address = 0x42) [Reset = 0x00]

INT_LIVE1 is shown in Table 8-142.

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Live interrupt readback.

Table 8-142 INT_LIVE1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3INT_LIVE1R0bInterrupt due to Headset Insert Detection .
0b = No interrupt
1b = Interrupt
2INT_LIVE1R0bInterrupt due to Headset Remove Detection .
0b = No interrupt
1b = Interrupt
2INT_LIVE1R0bInterrupt due to Headset hook(button) .
0b = No interrupt
1b = Interrupt
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0b

8.2.35 INT_LIVE2 Register (Address = 0x43) [Reset = 0x00]

INT_LIVE2 is shown in Table 8-143.

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Live interrupt readback.

Table 8-143 INT_LIVE2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE2R0bInterrupt due to GPA up threshold fault .
0b = No interrupt
1b = Interrupt
6INT_LIVE2R0bInterrupt due to GPA low threshold fault
0b = No interrupt
1b = Interrupt
5INT_LIVE2R0bInterrupt due to VAD power up detect .
0b = No interrupt
1b = Interrupt
4INT_LIVE2R0bInterrupt due to VAD power down detect .
0b = No interrupt
1b = Interrupt
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

8.2.36 DIAG_CFG8 Register (Address = 0x4E) [Reset = 0xBA]

DIAG_CFG8 is shown in Table 8-144.

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Table 8-144 DIAG_CFG8 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_UP_THRS_FLT_THRES[7:0]R/W10111010bGeneral Purpose Analog High Threshold
Default = ~ 2.6V
nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V)

8.2.37 DIAG_CFG9 Register (Address = 0x4F) [Reset = 0x4B]

DIAG_CFG9 is shown in Table 8-145.

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Table 8-145 DIAG_CFG9 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_LOW_THRS_FLT_THRES[7:0]R/W01001011bGeneral Purpose Analog Low Threshold
Default = ~ 0.2V
nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V)

8.2.38 DIAG_CFG14 Register (Address = 0x54) [Reset = 0x48]

DIAG_CFG14 is shown in Table 8-146.

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Table 8-146 DIAG_CFG14 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5AVDD_FILT_SEL[1:0]R/W10bAVDD filter select
0d = 3.5MHz
1d = 200kHz
2d = 100kHz
3d = No filter
4RESERVEDR/W0bReserved bit; Write only reset value
3-2VBAT_FILT_SEL[1:0]R/W10bVBAT filter select
0d = 3.5MHz
1d = 200kHz
2d = 100kHz
3d = No filter
1RESERVEDR/W0bReserved bit; Write only reset value
0RESERVEDR/W0bReserved bit; Write only reset value

8.2.39 DIAGDATA_CFG Register (Address = 0x55) [Reset = 0x00]

DIAGDATA_CFG is shown in Table 8-147.

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Table 8-147 DIAGDATA_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0000bReserved bits; Write only reset values
3IADC_DATA_IN_DIAG_REGSR/W0bIADC channel data in diagnostics channel data registers
0b= Disabled
1b= Enabled
2HOLD_IADC_DATAR/W0bHold IADC data update during register readback
0b= Data update is not held, Data register is continuously updated
1b= Data update is held, Data register readback can be done
1OVRD_VBAT_TEMP_DATAR/W0bOverride VBAT and TEMP data
0b= Override Disabled
1b= Override Enabled
0HOLD_SAR_DATAR/W0bHold SAR data update during register readback
0b= Data update is not held, Data register is continuously updated
1b= Data update is held, Data register readback can be done

8.2.40 DIAG_MON_MSB_MBIAS Register (Address = 0x58) [Reset = 0x00]

DIAG_MON_MSB_MBIAS is shown in Table 8-148.

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Table 8-148 DIAG_MON_MSB_MBIAS Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_MBIAS[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.2.41 DIAG_MON_LSB_MBIAS Register (Address = 0x59) [Reset = 0x01]

DIAG_MON_LSB_MBIAS is shown in Table 8-149.

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Table 8-149 DIAG_MON_LSB_MBIAS Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_MBIAS[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0001bChannel ID

8.2.42 DIAG_MON_MSB_OUT1P Register (Address = 0x62) [Reset = 0x00]

DIAG_MON_MSB_OUT1P is shown in Table 8-150.

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Table 8-150 DIAG_MON_MSB_OUT1P Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_OUT_CH1P[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.2.43 DIAG_MON_LSB_OUT1P Register (Address = 0x63) [Reset = 0x06]

DIAG_MON_LSB_OUT1P is shown in Table 8-151.

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Table 8-151 DIAG_MON_LSB_OUT1P Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_OUT_CH1P[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0110bChannel ID

8.2.44 DIAG_MON_MSB_OUT1M Register (Address = 0x64) [Reset = 0x00]

DIAG_MON_MSB_OUT1M is shown in Table 8-152.

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Table 8-152 DIAG_MON_MSB_OUT1M Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_OUT_CH1N[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.2.45 DIAG_MON_LSB_OUT1M Register (Address = 0x65) [Reset = 0x07]

DIAG_MON_LSB_OUT1M is shown in Table 8-153.

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Table 8-153 DIAG_MON_LSB_OUT1M Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_OUT_CH1N[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0111bChannel ID

8.2.46 DIAG_MON_MSB_OUT2P Register (Address = 0x66) [Reset = 0x00]

DIAG_MON_MSB_OUT2P is shown in Table 8-154.

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Table 8-154 DIAG_MON_MSB_OUT2P Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_OUT_CH2P[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.2.47 DIAG_MON_LSB_OUT2P Register (Address = 0x67) [Reset = 0x08]

DIAG_MON_LSB_OUT2P is shown in Table 8-155.

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Table 8-155 DIAG_MON_LSB_OUT2P Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_OUT_CH2P[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1000bChannel ID

8.2.48 DIAG_MON_MSB_OUT2M Register (Address = 0x68) [Reset = 0x00]

DIAG_MON_MSB_OUT2M is shown in Table 8-156.

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Table 8-156 DIAG_MON_MSB_OUT2M Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_OUT_CH2N[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.2.49 DIAG_MON_LSB_OUT2M Register (Address = 0x69) [Reset = 0x09]

DIAG_MON_LSB_OUT2M is shown in Table 8-157.

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Table 8-157 DIAG_MON_LSB_OUT2M Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_OUT_CH2N[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1001bChannel ID

8.2.50 DIAG_MON_MSB_TEMP Register (Address = 0x6A) [Reset = 0x00]

DIAG_MON_MSB_TEMP is shown in Table 8-158.

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Table 8-158 DIAG_MON_MSB_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_TEMP[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.2.51 DIAG_MON_LSB_TEMP Register (Address = 0x6B) [Reset = 0x0A]

DIAG_MON_LSB_TEMP is shown in Table 8-159.

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Table 8-159 DIAG_MON_LSB_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_TEMP[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1010bChannel ID

8.2.52 DIAG_MON_MSB_MBIAS_LOAD Register (Address = 0x6C) [Reset = 0x00]

DIAG_MON_MSB_MBIAS_LOAD is shown in Table 8-160.

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Table 8-160 DIAG_MON_MSB_MBIAS_LOAD Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_MBIAS_LOAD[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.2.53 DIAG_MON_LSB_MBIAS_LOAD Register (Address = 0x6D) [Reset = 0x0B]

DIAG_MON_LSB_MBIAS_LOAD is shown in Table 8-161.

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Table 8-161 DIAG_MON_LSB_MBIAS_LOAD Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_MBIAS_LOAD[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1011bChannel ID

8.2.54 DIAG_MON_MSB_AVDD Register (Address = 0x6E) [Reset = 0x00]

DIAG_MON_MSB_AVDD is shown in Table 8-162.

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Table 8-162 DIAG_MON_MSB_AVDD Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_AVDD[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.2.55 DIAG_MON_LSB_AVDD Register (Address = 0x6F) [Reset = 0x0C]

DIAG_MON_LSB_AVDD is shown in Table 8-163.

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Table 8-163 DIAG_MON_LSB_AVDD Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_AVDD[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1100bChannel ID

8.2.56 DIAG_MON_MSB_GPA Register (Address = 0x70) [Reset = 0x00]

DIAG_MON_MSB_GPA is shown in Table 8-164.

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Table 8-164 DIAG_MON_MSB_GPA Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_GPA[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

8.2.57 DIAG_MON_LSB_GPA Register (Address = 0x71) [Reset = 0x0D]

DIAG_MON_LSB_GPA is shown in Table 8-165.

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Table 8-165 DIAG_MON_LSB_GPA Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_GPA[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1101bChannel ID