This section describes the necessary
steps to configure the TAC5111-Q1 for this specific application. The
following steps provide a sequence of items that must be executed in the time
between powering the device up and reading data from the device or transitioning
from one mode to another mode of operation.
- Apply power to the device:
- Power up the IOVDD and AVDD power supplies
- Wait for at least 1ms to
allow the device to initialize the internal registers.
- The device now goes into sleep mode (low-power mode
< 10 µA)
- Transition from sleep mode to active mode whenever required for
the operation:
- Wake up the device by writing to P0_R2 to disable sleep
mode
- Wait for at least 1 ms to allow the device to complete
the internal wake-up sequence
- Override the default configuration registers or
programmable coefficients value as required (this step is optional)
- Enable all desired input channels by writing to
P0_R118
- Enable all desired audio serial interface input/output
channels by writing to P0_R40 to P0_R47 for DAC and P0_R30 to P0_R37 for
ADC
- Power-up the ADC, DAC and MICBIAS by writing to
P0_R120
- Apply FSYNC and BCLK with the desired output sample
rates and the BCLK to FSYNC ratio
This specific step
can be done at any point in the sequence after step a.
See the Section 7.3.2 section for supported sample rates and the BCLK to FSYNC
ratio.
- The device recording data is now sent to the host
processor using the TDM audio serial data bus and playback data from TDM
is now played on the lineout
- Transition from active mode to sleep mode (again) as required
in the system for low-power operation:
- Enter sleep mode by writing to P0_R2 to enable sleep
mode
- Wait at least 6 ms (when FSYNC = 48 kHz) for the volume
to ramp down and for all blocks to power down
- Read P0_R122 to check the device shutdown and sleep
mode status
- If the device P0_R122_D[7:5] status bit is 3'b100 then
stop FSYNC and BCLK in the system
- The device now goes into sleep mode (low-power mode
< 10 µA) and retains all register values
- Transition from sleep mode to active mode (again) as required
for the recording operation:
- Wake up the device by writing to P0_R2 to disable sleep
mode
- Wait at least 1 ms to allow the device to complete the
internal wake-up sequence
- Apply FSYNC and BCLK with the desired output sample
rates and the BCLK to FSYNC ratio
- The device recording data
is now sent to the host processor using the TDM audio serial data bus
and playback data from TDM is now played on the lineout
- Repeat step 4 and step 5 as required for mode transitions