SLASFC3 January 2024 TAC5111-Q1
ADVANCE INFORMATION
The device consists of two pairs of analog output pins (OUTxP and OUTxM) that can be configured as differential inputs or single-ended outputs for playback channels. The device supports simultaneous playback of up to four channels of single-ended output or up to two channel differential output using the high-performance multichannel DAC. Table 7-9 shows the input source selection for the playback channels.
P0_R100_D[7:5] : OUT1x_SRC[2:0] | OUT1P/OUT1M Source Selection |
---|---|
000 (default) | Output driver disabled |
001 | DAC signal chain |
010 | Analog bypass signal chain |
011 | Mixing of DAC and analog bypass signal chains |
100 | OUT1P for DAC and OUT1M for analog bypass signal chain |
101 | OUT1P for analog bypass and OUT1M for DAC signal chain. |
11x | Reserved. Do not use this setting. |
Similarly, the input source selection setting for output channel 2 can be configured using the OUT2x_SRC[2:0] (P0_R107_D[7:5]) register bits.
The TAC5111-Q1 supports up to 2-channel differential output, up to 2-channel pseudo-differential output, and up to 4-channel single-ended output. Each of the output channels can be independently configured for differential or single-ended output.
Table 7-10 shows the configuration modes for the output pins
P0_R100_D[4:2] : OUT1x_CFG[2:0] | OUT1P/OUT1M Pin Configuration |
---|---|
000 (default) | OUT1P/OUT1M as a differential pair |
001 | OUT1P and OUT1M as independent single-ended outputs |
010 | Mono Single Ended output on OUT1P only |
011 | Mono Single Ended output on OUT1M only |
100 | Pseudo-differential output with OUT1P as signal and OUT1M as VCOM |
101 | Pseudo differential output with OUT1P as signal, OUT1M as VCOM and OUT2M as VCOM sense. |
110 | Pseudo differential output with OUT1M as signal and OUT1P as VCOM |
111 | Reserved. Do not use this setting. |
Similarly, the output pin configuration for output channel 2 can be done using the OUT2x_CFG[2:0] (P0_R107_D[4:2]) register bits.
The TAC5111-Q1 can support a variety of loads including headphone, lineout, and receiver amplifiers. Load drive configurations are available for each pin independently. OUT1P_DRIVE[1:0] (OUT1x_CFG[7:6]) configures the load drive capability for the OUT1P pin. OUT1M_DRIVE[1:0], OUT2P_DRIVE[1:0], OUT2M_DRIVE[1:0] are the output drive control for OUT1M, OUT2P and OUT2M respectively.