SLASFC2 January   2024 TAC5112-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 6.14 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Input Channel Configurations
      4. 7.3.4 Output Channel Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Programmable Microphone Bias
      7. 7.3.7 Signal-Chain Processing
        1. 7.3.7.1 ADC Signal-Chain
          1. 7.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.1.2 Programmable Channel Gain Calibration
          3. 7.3.7.1.3 Programmable Channel Phase Calibration
          4. 7.3.7.1.4 Programmable Digital High-Pass Filter
          5. 7.3.7.1.5 Programmable Digital Biquad Filters
          6. 7.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 7.3.7.1.7 Configurable Digital Decimation Filters
            1. 7.3.7.1.7.1 Linear Phase Filters
              1. 7.3.7.1.7.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 7.3.7.1.7.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 7.3.7.1.7.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 7.3.7.1.7.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 7.3.7.1.7.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 7.3.7.1.7.1.6 Sampling Rate: 384kHz or 352.8kHz
        2. 7.3.7.2 DAC Signal-Chain
          1. 7.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.2.2 Programmable Channel Gain Calibration
          3. 7.3.7.2.3 Programmable Digital High-Pass Filter
          4. 7.3.7.2.4 Programmable Digital Biquad Filters
          5. 7.3.7.2.5 Programmable Digital Mixer
          6. 7.3.7.2.6 Configurable Digital Interpolation Filters
            1. 7.3.7.2.6.1 Linear Phase Filters
              1. 7.3.7.2.6.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 7.3.7.2.6.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 7.3.7.2.6.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 7.3.7.2.6.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 7.3.7.2.6.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 7.3.7.2.6.1.6 Sampling Rate: 384kHz or 352.8kHz
      8. 7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
  9. 8 Register Maps
    1. 8.1 TAC5212 Registers
    2. 8.2 TAC5212 Registers
    3. 8.3 TAC5212 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Timing Requirements: TDM, I2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see for timing diagram
MIN NOM MAX UNIT
t(BCLK) BCLK period 40 ns
tH(BCLK) BCLK high pulse duration (1) 18 ns
tL(BCLK) BCLK low pulse duration (1) 18 ns
tSU(FSYNC) FSYNC setup time 8 ns
tHLD(FSYNC) FSYNC hold time 8 ns
tSU(DIN) DIN setup time 8 ns
tHLD(DIN) DIN hold time 8 ns
tr(BCLK) BCLK rise time 10% - 90% rise time 10 ns
tf(BCLK) BCLK fall time 90% - 10% fall time 10 ns
(1) The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.