SLASF28A
December 2023 – November 2024
TAC5142
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements: TDM, I2S or LJ Interface
6.7
Switching Characteristics: TDM, I2S or LJ Interface
6.8
Timing Diagrams
6.9
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Hardware Control
7.3.2
Audio Serial Interfaces
7.3.2.1
Time Division Multiplexed Audio (TDM) Interface
7.3.2.2
Inter IC Sound (I2S) Interface
7.3.2.3
Left-Justified (LJ) Interface
7.3.3
Phase-Locked Loop (PLL) and Clock Generation
7.3.4
Analog Input and Output Configurations
7.3.5
Reference Voltage
7.3.6
Integrated Microphone Bias
7.3.7
ADC Signal-Chain
7.3.7.1
Digital High-Pass Filter
7.3.7.2
Configurable Digital Decimation Filters
7.3.7.2.1
Linear-phase filters
7.3.7.2.1.1
Sampling Rate: 8kHz or 7.35kHz
7.3.7.2.1.2
Sampling Rate: 16kHz or 14.7kHz
7.3.7.2.1.3
Sampling Rate: 24kHz or 22.05kHz
7.3.7.2.1.4
Sampling Rate: 32kHz or 29.4kHz
7.3.7.2.1.5
Sampling Rate: 48kHz or 44.1kHz
7.3.7.2.1.6
Sampling Rate: 96kHz or 88.2kHz
7.3.7.2.1.7
Sampling Rate: 192kHz or 176.4kHz
7.3.7.2.2
Low-latency Filters
7.3.7.2.2.1
Sampling Rate: 24kHz or 22.05kHz
7.3.7.2.2.2
Sampling Rate: 32kHz or 29.4kHz
7.3.7.2.2.3
Sampling Rate: 48kHz or 44.1kHz
7.3.7.2.2.4
Sampling Rate: 96kHz or 88.2kHz
7.3.7.2.2.5
Sampling Rate: 192kHz or 176.4kHz
7.3.8
DAC Signal-Chain
7.3.8.1
Digital Interpolation Filters
7.3.8.1.1
Linear-phase filters
7.3.8.1.1.1
Sampling Rate: 8kHz or 7.35kHz
7.3.8.1.1.2
Sampling Rate: 16kHz or 14.7kHz
7.3.8.1.1.3
Sampling Rate: 24kHz or 22.05kHz
7.3.8.1.1.4
Sampling Rate: 32kHz or 29.4kHz
7.3.8.1.1.5
Sampling Rate: 48kHz or 44.1kHz
7.3.8.1.1.6
Sampling Rate: 96kHz or 88.2kHz
7.3.8.1.1.7
Sampling Rate: 192kHz or 176.4kHz
7.3.8.1.2
Low-latency Filters
7.3.8.1.2.1
Sampling Rate: 24kHz or 22.05kHz
7.3.8.1.2.2
Sampling Rate: 32kHz or 29.4kHz
7.3.8.1.2.3
Sampling Rate: 48kHz or 44.1kHz
7.3.8.1.2.4
Sampling Rate: 96kHz or 88.2kHz
7.3.8.1.2.5
Sampling Rate: 192kHz or 176.4kHz
7.4
Device Functional Modes
7.4.1
Active Mode
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Application
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
8.2.4
Application Performance Plots
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGE|24
MPQF124G
Thermal pad, mechanical data (Package|Pins)
RGE|24
QFND808
Orderable Information
slasf28a_oa
slasf28a_pm
1
Features
Stereo audio ADC Channels
Performance:
Line/Microphone differential input dynamic range:
103
dB
Differential input THD+N:
–91
dB
Input voltage:
Differential, 2V
RMS
full-scale inputs
Single-ended, 1V
RMS
full-scale inputs
ADC sample rates (f
S
) = 8kHz to 192kHz
Digital HPF with configurable cut-off frequency:
1Hz or 12Hz, at 48kHz sampling rate
Low noise microphone bias
Stereo audio DAC Channels
Performance:
DAC to differential line-out dynamic range:
110
dB
DAC to pseudo-differential headphone-out dynamic range:
107
dB
THD+N: –100 dB
Output voltage:
Differential line-out/receiver, 2V
RMS
full-scale
Pseudo-differential headphone, 1V
RMS
full-scale
Single-ended line-out, 1V
RMS
full-scale
DAC sample rates (f
s
) = 8kHz to 192kHz
Common Features
Pin or Hardware Control
Audio Serial Interface
Format: TDM, I
2
S, or Left-justified (LJ)
Bus Controller and Target Modes
Configurable TDM Slots
Word Length: Selectable 24 or 32 Bits
Pin-selectable digital decimation/interpolation filter options:
Linear-phase or Low-latency
Integrated PLL
Auto clock & sample rate detection
Interrupt output on clock error
Single Supply Operation AVDD: 1.8V or 3.3V
I/O Supply Operation: 1.8V or 3.3V
Temperature grade 1: –40°C ≤ T
A
≤ +125°C