SLASF27A December   2023  – November 2024 TAC5242

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
        3. 7.3.2.3 Left-Justified (LJ) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Analog Input and Output Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Integrated Microphone Bias
      7. 7.3.7 ADC Signal-Chain
        1. 7.3.7.1 Digital High-Pass Filter
        2. 7.3.7.2 Configurable Digital Decimation Filters
          1. 7.3.7.2.1 Linear-phase filters
            1. 7.3.7.2.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 7.3.7.2.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 7.3.7.2.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 7.3.7.2.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 7.3.7.2.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 7.3.7.2.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 7.3.7.2.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 7.3.7.2.2 Low-latency Filters
            1. 7.3.7.2.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 7.3.7.2.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 7.3.7.2.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 7.3.7.2.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 7.3.7.2.2.5 Sampling Rate: 192kHz or 176.4kHz
      8. 7.3.8 DAC Signal-Chain
        1. 7.3.8.1 Digital Interpolation Filters
          1. 7.3.8.1.1 Linear-phase filters
            1. 7.3.8.1.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 7.3.8.1.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 7.3.8.1.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 7.3.8.1.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 7.3.8.1.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 7.3.8.1.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 7.3.8.1.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 7.3.8.1.2 Low-latency Filters
            1. 7.3.8.1.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 7.3.8.1.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 7.3.8.1.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 7.3.8.1.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 7.3.8.1.2.5 Sampling Rate: 192kHz or 176.4kHz
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2.3 Left-Justified (LJ) Interface

The standard LJ protocol is defined for only two channels: left and right. In LJ mode, the MSB of the left slot 0 is transmitted and received in the same BCLK cycle after the rising edge of FSYNC. The MSB of the right slot 0 is transmitted and received in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK and received on the rising edge of BCLK. Figure 7-5 illustrates the protocol timing for LJ operation in the target mode of operation.

TAC5242 LJ Mode Standard Protocol Timing (MD0 shorted to AVDD with 22 kOhm) in Target ModeFigure 7-5 LJ Mode Standard Protocol Timing (MD0 shorted to AVDD with 22 kOhm) in Target Mode

For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or equal to the number of active input and output channels (including left and right slots) times the configured word length of the input and output channel data.