SLASF27 December 2023 TAC5242
ADVANCE INFORMATION
The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the ADC and DAC modulators and digital filter engine, as well as other control blocks.
In target mode of operation, the device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 8-4 and Table 8-5 list the supported FSYNC and BCLK frequencies.
BCLK TO FSYNC RATIO | BCLK (MHz) | ||||||
---|---|---|---|---|---|---|---|
FSYNC (8 kHz) |
FSYNC (16 kHz) |
FSYNC (24 kHz) |
FSYNC (32 kHz) |
FSYNC (48 kHz) |
FSYNC (96 kHz) |
FSYNC (192 kHz) |
|
16 | Reserved | 0.256 | 0.384 | 0.512 | 0.768 | 1.536 | 3.072 |
24 | Reserved | 0.384 | 0.576 | 0.768 | 1.152 | 2.304 | 4.608 |
32 | 0.256 | 0.512 | 0.768 | 1.024 | 1.536 | 3.072 | 6.144 |
48 | 0.384 | 0.768 | 1.152 | 1.536 | 2.304 | 4.608 | 9.216 |
64 | 0.512 | 1.024 | 1.536 | 2.048 | 3.072 | 6.144 | 12.288 |
96 | 0.768 | 1.536 | 2.304 | 3.072 | 4.608 | 9.216 | 18.432 |
128 | 1.024 | 2.048 | 3.072 | 4.096 | 6.144 | 12.288 | 24.576 |
192 | 1.536 | 3.072 | 4.608 | 6.144 | 9.216 | 18.432 | Reserved |
256 | 2.048 | 4.096 | 6.144 | 8.192 | 12.288 | 24.576 | Reserved |
384 | 3.072 | 6.144 | 9.216 | 12.288 | 18.432 | Reserved | Reserved |
512 | 4.096 | 8.192 | 12.288 | 16.384 | 24.576 | Reserved | Reserved |
BCLK TO FSYNC RATIO | BCLK (MHz) | ||||||
---|---|---|---|---|---|---|---|
FSYNC (7.35 kHz) |
FSYNC (14.7 kHz) |
FSYNC (22.05 kHz) |
FSYNC (29.4 kHz) |
FSYNC (44.1 kHz) |
FSYNC (88.2 kHz) |
FSYNC (176.4 kHz) |
|
16 | Reserved | Reserved | 0.3528 | 0.4704 | 0.7056 | 1.4112 | 2.8224 |
24 | Reserved | 0.3528 | 0.5292 | 0.7056 | 1.0584 | 2.1168 | 4.2336 |
32 | Reserved | 0.4704 | 0.7056 | 0.9408 | 1.4112 | 2.8224 | 5.6448 |
48 | 0.3528 | 0.7056 | 1.0584 | 1.4112 | 2.1168 | 4.2336 | 8.4672 |
64 | 0.4704 | 0.9408 | 1.4112 | 1.8816 | 2.8224 | 5.6448 | 11.2896 |
96 | 0.7056 | 1.4112 | 2.1168 | 2.8224 | 4.2336 | 8.4672 | 16.9344 |
128 | 0.9408 | 1.8816 | 2.8224 | 3.7632 | 5.6448 | 11.2896 | 22.5792 |
192 | 1.4112 | 2.8224 | 4.2336 | 5.6448 | 8.4672 | 16.9344 | Reserved |
256 | 1.8816 | 3.7632 | 5.6448 | 7.5264 | 11.2896 | 22.5792 | Reserved |
384 | 2.8224 | 5.6448 | 8.4672 | 11.2896 | 16.9344 | Reserved | Reserved |
512 | 3.7632 | 7.5264 | 11.2896 | 15.0528 | 22.5792 | Reserved | Reserved |
In the controller mode of operation, the device uses the MD3 pin (as the system clock, CCLK) as the reference input clock source. The device provides flexibility in FSYNC selection with a supported system clock frequency option of either 256 × fS or 128 × fS or a fixed 48/44.1KSPS or 96/88.2KSPS as configured using the MD1 and MD2 pins. Table 8-6 shows the FSYNC and BCLK selection for the controller mode using the MD1 and MD2 pins.
MD1 | MD2 | SYSTEM CLOCK SELECTION (Valid for Master Mode Only) |
---|---|---|
LOW | LOW | FSYNC =
CCLK/256 I2S Mode: BCLK = 64*fS TDM Mode: |
LOW | HIGH | FSYNC =
CCLK/128 I2S Mode: BCLK = 64*fS TDM Mode: |
HIGH | LOW | FSYNC = 96/88.2KSPS;
I2S Mode: BCLK = 64*fS TDM Mode: BCLK = 128*fS |
HIGH | HIGH | FSYNC = 48/44.1KSPS;
I2S Mode: BCLK = 64*fS TDM Mode: BCLK = 128*fS |
See Table 8-2 for the MD1, MD2 and MD3 pin function in the target mode of operation.