SLASF27A December   2023  – November 2024 TAC5242

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
        3. 7.3.2.3 Left-Justified (LJ) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Analog Input and Output Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Integrated Microphone Bias
      7. 7.3.7 ADC Signal-Chain
        1. 7.3.7.1 Digital High-Pass Filter
        2. 7.3.7.2 Configurable Digital Decimation Filters
          1. 7.3.7.2.1 Linear-phase filters
            1. 7.3.7.2.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 7.3.7.2.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 7.3.7.2.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 7.3.7.2.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 7.3.7.2.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 7.3.7.2.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 7.3.7.2.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 7.3.7.2.2 Low-latency Filters
            1. 7.3.7.2.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 7.3.7.2.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 7.3.7.2.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 7.3.7.2.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 7.3.7.2.2.5 Sampling Rate: 192kHz or 176.4kHz
      8. 7.3.8 DAC Signal-Chain
        1. 7.3.8.1 Digital Interpolation Filters
          1. 7.3.8.1.1 Linear-phase filters
            1. 7.3.8.1.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 7.3.8.1.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 7.3.8.1.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 7.3.8.1.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 7.3.8.1.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 7.3.8.1.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 7.3.8.1.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 7.3.8.1.2 Low-latency Filters
            1. 7.3.8.1.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 7.3.8.1.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 7.3.8.1.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 7.3.8.1.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 7.3.8.1.2.5 Sampling Rate: 192kHz or 176.4kHz
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Phase-Locked Loop (PLL) and Clock Generation

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the ADC and DAC modulators and digital filter engine, as well as other control blocks.

In the target mode of operation, the device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 7-5 to Table 7-8 list the supported FSYNC and BCLK frequencies depending on the IOVDD Supply.

Table 7-5 Supported FSYNC (Multiples or Submultiples of 48kHz) and BCLK Frequencies (IOVDD - 3.3V Operation)
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC
(8 kHz)		FSYNC
(16 kHz)		FSYNC
(24 kHz)		FSYNC
(32 kHz)		FSYNC
(48 kHz)		FSYNC
(96 kHz)		FSYNC
(192 kHz)
16Reserved0.2560.3840.5120.7681.5363.072
24Reserved0.3840.5760.7681.1522.3044.608
320.2560.5120.7681.0241.5363.0726.144
480.3840.7681.1521.5362.3044.6089.216
640.5121.0241.5362.0483.0726.14412.288
960.7681.5362.3043.0724.6089.21618.432
1281.0242.0483.0724.0966.14412.28824.576
1921.5363.0724.6086.1449.21618.432Reserved
2562.0484.0966.1448.19212.28824.576Reserved
3843.0726.1449.21612.28818.432ReservedReserved
5124.0968.19212.28816.38424.576ReservedReserved
Table 7-6 Supported FSYNC (Multiples or Submultiples of 44.1kHz) and BCLK Frequencies (IOVDD - 3.3V Operation)
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC
(7.35 kHz)		FSYNC
(14.7 kHz)		FSYNC
(22.05 kHz)		FSYNC
(29.4 kHz)		FSYNC
(44.1 kHz)		FSYNC
(88.2 kHz)		FSYNC
(176.4 kHz)
16ReservedReserved0.35280.47040.70561.41122.8224
24Reserved0.35280.52920.70561.05842.11684.2336
32Reserved0.47040.70560.94081.41122.82245.6448
480.35280.70561.05841.41122.11684.23368.4672
640.47040.94081.41121.88162.82245.644811.2896
960.70561.41122.11682.82244.23368.467216.9344
1280.94081.88162.82243.76325.644811.289622.5792
1921.41122.82244.23365.64488.467216.9344Reserved
2561.88163.76325.64487.526411.289622.5792Reserved
3842.82245.64488.467211.289616.9344ReservedReserved
5123.76327.526411.289615.052822.5792ReservedReserved
Table 7-7 Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies (IOVDD - 1.8V Operation)
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC
(8 kHz)		FSYNC
(16 kHz)		FSYNC
(24 kHz)		FSYNC
(32 kHz)		FSYNC
(48 kHz)		FSYNC
(96 kHz)		FSYNC
(192 kHz)
16Reserved0.2560.3840.5120.7681.5363.072
24Reserved0.3840.5760.7681.1522.3044.608
320.2560.5120.7681.0241.5363.0726.144
480.3840.7681.1521.5362.3044.6089.216
640.5121.0241.5362.0483.0726.14412.288
960.7681.5362.3043.0724.6089.216Reserved
1281.0242.0483.0724.0966.14412.288Reserved
1921.5363.0724.6086.1449.216ReservedReserved
2562.0484.0966.1448.19212.288ReservedReserved
3843.0726.1449.21612.288ReservedReservedReserved
5124.0968.19212.288ReservedReservedReservedReserved
Table 7-8 Supported FSYNC (Multiples or Submultiples of 44.1kHz) and BCLK Frequencies (IOVDD - 1.8V Operation)
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC
(7.35 kHz)		FSYNC
(14.7 kHz)		FSYNC
(22.05 kHz)		FSYNC
(29.4 kHz)		FSYNC
(44.1 kHz)		FSYNC
(88.2 kHz)		FSYNC
(176.4 kHz)
16ReservedReserved0.35280.47040.70561.41122.8224
24Reserved0.35280.52920.70561.05842.11684.2336
32Reserved0.47040.70560.94081.41122.82245.6448
480.35280.70561.05841.41122.11684.23368.4672
640.47040.94081.41121.88162.82245.644811.2896
960.70561.41122.11682.82244.23368.4672Reserved
1280.94081.88162.82243.76325.644811.2896Reserved
1921.41122.82244.23365.64488.4672ReservedReserved
2561.88163.76325.64487.526411.2896ReservedReserved
3842.82245.64488.467211.2896ReservedReservedReserved
5123.76327.526411.2896ReservedReservedReservedReserved

In the controller mode of operation, the device uses the MD3 pin, as the system clock, and CCLK as the reference input clock source. In target mode of operation, the MD3 pin function is described in Table 7-4 and Table 7-11.

The device provides flexibility in FSYNC selection with a supported system clock frequency option of either 256×fS or 128×fS or a fixed 48/44.1kHz or 96/88.2kHz as configured using the MD1 and MD2 pins. Table 7-9 shows the FSYNC and BCLK selection for the controller mode using the MD1 and MD2 pins.

Table 7-9 System Clock Selection for the Controller Mode
MD2MD1SYSTEM CLOCK SELECTION (Valid for Controller Mode Only)
FSYNCBCLK TO FSYNC RATIO
I2S MODETDM MODE
LOWLOWCCLK/25664256 for FSYNC ≤ 48kHz,

128 for 48kHz < FSYNC ≤ 96kHz, and

64 for FSYNC > 96kHz

LOWHIGHCCLK/128
HIGHLOW96/88.2kHz128
HIGHHIGH48/44.1kHz256

See Table 7-3 for the MD1 and MD2 pin functions in the target mode of operation. In the controller mode of operation, AVDD = 3.3V and Word-Length = 32 and a linear-phase decimation/interpolation filter is applicable.