SLASF27 December 2023 TAC5242
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
td(SDOUT-BCLK) | BCLK to SDOUT delay | 50% of BCLK to 50% of SDOUT, IOVDD = 1.8 V | 18 | ns | ||
50% of BCLK to 50% of SDOUT, IOVDD = 3.3 V | 14 | |||||
td(SDOUT-FSYNC) | FSYNC to SDOUT delay in TDM or LJ mode (for MSB data with TX_OFFSET = 0) | 50% of FSYNC to 50% of SDOUT, IOVDD = 1.8 V | 18 | ns | ||
50% of FSYNC to 50% of SDOUT, IOVDD = 3.3 V | 14 | |||||
f(BCLK) | BCLK output clock frequency; master mode (1) | 24.576 | MHz | |||
tH(BCLK) | BCLK high pulse duration; master mode | IOVDD = 1.8 V | 14 | ns | ||
IOVDD = 3.3 V | 14 | |||||
tL(BCLK) | BCLK low pulse duration; master mode | IOVDD = 1.8 V | 14 | ns | ||
IOVDD = 3.3 V | 14 | |||||
td(FSYNC) | BCLK to FSYNC delay; master mode | 50% of BCLK to 50% of FSYNC, IOVDD = 1.8 V | 18 | ns | ||
50% of BCLK to 50% of FSYNC, IOVDD = 3.3 V | 14 | |||||
tr(BCLK) | BCLK rise time; master mode | 10% - 90% rise time, IOVDD = 1.8 V | 10 | ns | ||
10% - 90% rise time, IOVDD = 3.3 V | 10 | |||||
tf(BCLK) | BCLK fall time; master mode | 90% - 10% fall time, IOVDD = 1.8 V | 8 | ns | ||
90% - 10% fall time, IOVDD = 3.3 V | 8 |