SLASF36A January 2024 – December 2024 TAC5311-Q1
PRODUCTION DATA
In addition to the gain calibration, the phase delay in each record channel can be finely calibrated or adjusted in steps of one modulator clock cycle for a cycle range of 1 to 63 for the phase error. The modulator clock for analog and digital microphones is set independantly. For analog microphones, it is the clock used for ADC MOD CLK, and is 3.072MHz (the output data sample rate is multiples or submultiples of 48kHz) or 2.8224MHz (the output data sample rate is multiples or submultiples of 44.1 kHz) in default configurations. For power savings, the ADC modulator clock can also be reduced to 1.536MHz (the output data sample rate is multiples or submultiples of 48kHz) or 1.4112MHz (the output data sample rate is multiples or submultiples of 44.1 kHz) by using ADC_CLK_BY2_MODE (B0_P78_D[7]) register bit. For the digital microphone use case, it is the clock used for PDM_CLK, and is also 3.072MHz (the output data sample rate is multiples or submultiples of 48kHz) or 2.8224MHz (the output data sample rate is multiples or submultiples of 44.1 kHz) in default configurations. User can configure the PDM_CLK using the PDM_CLK_CFG[1:0] (P0_R53_D[7:6]) register bits. The programmable channel phase calibration feature is very useful for many applications that must match the phase with fine resolution between each channel, including any phase mismatch across channels resulting from external components or microphones. Table 6-13 shows the available programmable options for channel phase calibration.
P0_R64_D[7:0] : CH1_PCAL[7:0] | CHANNEL PHASE CALIBRATION SETTING FOR INPUT CHANNEL 1 |
---|---|
0000 0000 = 0d (default) | Input channel 1 phase calibration with no delay |
0000 0001 = 1d | Input channel 1 phase calibration delay is set to one cycle of the modulator clock |
0000 0010 = 2d | Input channel 1 phase calibration delay is set to two cycles of the modulator clock |
… | … |
1111 1110 = 254d | Input channel 1 phase calibration delay is set to 254 cycles of the modulator clock |
1111 1111 = 255d | Input channel 1 phase calibration delay is set to 255 cycles of the modulator clock |
Similarly, the channel phase calibration setting for input channel 2 to channel 8 can be configured using the using the ADC_CH2_PCAL (P0_R89_D[7:2]) to ADC_CH4_PCAL (P0_R97_D[7:2]) register bits, respectively.
By default, the phase calibration is enabled for both analog and digital microphone channels. This can be changed to only analog or only digital microphones through the PCAL_ANA_DIG_SEL (P0_R84_D[1:0]) register bits. When using analog input and PDM input together for simulatneous conversion, there is a limit on the available phase calibration options for the analog channels when analog and PDM clocks are different. When using ADC MOD CLK = 1.536MHz or 1.4112MHz and PDM_CLK = 6.144MHz or 5.6448MHz, phase calibration delays of only 1 to 16 are supported for the analog channels. When using ADC MOD CLK = 3.072MHz or 2.8224 and PDM_CLK = 6.144MHz or 5.6448MHz, phase calibration delays of only 1 to 32 are supported for the analog channels. When using ADC MOD CLK = 1.536MHz or 1.4112MHz and PDM_CLK = 3.072MHz or 2.8224MHz also, phase calibration delays of only 1 to 32 are supported for the analog channels.