SLASF33 January   2024 TAC5412-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements: I2C Interface
    8. 5.8  Switching Characteristics: I2C Interface
    9. 5.9  Timing Requirements: SPI Interface
    10. 5.10 Switching Characteristics: SPI Interface
    11. 5.11 Timing Requirements: TDM, I2S or LJ Interface
    12. 5.12 Switching Characteristics: TDM, I2S or LJ Interface
    13. 5.13 Timing Requirements: PDM Digital Microphone Interface
    14. 5.14 Switching Characteristics: PDM Digial Microphone Interface
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
      2. 6.3.2  Using Multiple Devices With Shared Buses
      3. 6.3.3  Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4  Input Channel Configuration
      5. 6.3.5  Reference Voltage
      6. 6.3.6  Microphone Bias
      7. 6.3.7  Input DC Fault Diagnostics
        1. 6.3.7.1 Fault Conditions
          1. 6.3.7.1.1 Input Pin Short to Ground
          2. 6.3.7.1.2 Input Pin Short to MICBIAS
          3. 6.3.7.1.3 Open Inputs
          4. 6.3.7.1.4 Short Between INxP and INxM
          5. 6.3.7.1.5 Input Pin Overvoltage
          6. 6.3.7.1.6 Input Pin Short to VBAT_IN
        2. 6.3.7.2 Fault Reporting
          1. 6.3.7.2.1 Overcurrent and Overtemperature Protection
      8. 6.3.8  Signal-Chain Processing
        1. 6.3.8.1 ADC Signal-Chain
          1. 6.3.8.1.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.8.1.2 Programmable Channel Gain Calibration
          3. 6.3.8.1.3 Programmable Channel Phase Calibration
          4. 6.3.8.1.4 Programmable Digital High-Pass Filter
          5. 6.3.8.1.5 Programmable Digital Biquad Filters
          6. 6.3.8.1.6 Programmable Channel Summer and Digital Mixer
          7. 6.3.8.1.7 Configurable Digital Decimation Filters
            1. 6.3.8.1.7.1 Linear Phase Filters
              1. 6.3.8.1.7.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 6.3.8.1.7.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 6.3.8.1.7.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 6.3.8.1.7.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 6.3.8.1.7.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 6.3.8.1.7.1.6 Sampling Rate: 384kHz or 352.8kHz
      9. 6.3.9  DAC Signal-Chain
        1. 6.3.9.1 Programmable Channel Gain and Digital Volume Control
        2. 6.3.9.2 Programmable Channel Gain Calibration
        3. 6.3.9.3 Programmable Digital High-Pass Filter
        4. 6.3.9.4 Programmable Digital Biquad Filters
        5. 6.3.9.5 Programmable Digital Mixer
        6. 6.3.9.6 Configurable Digital Interpolation Filters
          1. 6.3.9.6.1 Linear Phase Filters
            1. 6.3.9.6.1.1 Sampling Rate: 16kHz or 14.7kHz
            2. 6.3.9.6.1.2 Sampling Rate: 24kHz or 22.05kHz
            3. 6.3.9.6.1.3 Sampling Rate: 32kHz or 29.4kHz
            4. 6.3.9.6.1.4 Sampling Rate: 48kHz or 44.1kHz
            5. 6.3.9.6.1.5 Sampling Rate: 96kHz or 88.2kHz
            6. 6.3.9.6.1.6 Sampling Rate: 384kHz or 352.8kHz
      10. 6.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
  8. 7 Register Maps
    1. 7.1 Page 0 Registers
    2. 7.2 Page 1 Registers
    3. 7.3 Page_3 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the TAC5412-Q1 on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S or left-justified protocols format, programmable data length options, very flexible controller-target configurability for bus clock lines, and the ability to communicate with multiple devices within a system directly.

The TAC5412-Q1 supports up to two ASI Interfaces. Secondary ASI Clock and Data Pins can be configured by setting GPIO's. Frame Sync of two ASI's must be synchronous.

The bus protocol TDM, I2S, or left-justified (LJ) format can be selected for primary ASI by using the PASI_FORMAT[1:0], P0_R26_D[7:6] register bits. As shown in Table 6-1 and.Table 6-2, these modes are all most significant byte (MSB)-first, pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16, 20, 24, or 32 bits by configuring the PASI_WLEN[1:0], P0_R26_D[5:4] register bits.

Table 6-1 Primary Audio Serial Interface Format
P0_R26_D[7:6] : PASI_FORMAT[1:0]PRIMARY AUDIO SERIAL INTERFACE FORMAT
00 (default)Time division multiplexing (TDM) mode
01Inter IC sound (I2S) mode
10Left-justified (LJ) mode
11Reserved (do not use this setting)
Table 6-2 Primary Audio Serial Interface Data Word-Length
P0_R7_D[5:4] : PASI_WLEN[1:0]PRIMARY AUDIO OUTPUT CHANNEL DATA WORD-LENGTH
00Data word-length set to 16 bits
01Data word-length set to 20 bits
10Data word-length set to 24 bits
11 (default)Data word-length set to 32 bits

The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio data across the serial bus. The number of bit-clock cycles in a frame must accommodate multiple device active output channels with the programmed data word length.

A frame consists of multiple time-division channel slots (up to 32) to allow all input/output channel audio data transmissions to be completed on the audio bus by a device or multiple devices sharing the same audio bus. The device supports up to eight input channels and eight output channels that can be configured on the primary ASI bus to place their audio data on bus slot 0 to slot 31. Table 6-3 lists the output channel-1 slot configuration settings. In I2S and LJ mode, the slots are divided into two sets, left-channel slots, and right-channel slots, as described in the Section 6.3.1.2.2 and Section 6.3.1.2.3 sections.

Table 6-3 Output Channel-1 Slot Assignment Settings
P0_R30_D[4:0] : PASI_TX_CH1_SLOT[4:0]OUTPUT CHANNEL 1 SLOT ASSIGNMENT
0 0000 = 0d (default)Slot 0 for TDM or left slot 0 for I2S, LJ.
0 0001 = 1dSlot 1 for TDM or left slot 1 for LJ.
……
0 1111 = 15dSlot 15 for TDM or left slot 15 for LJ.
1 0000 = 32dSlot 16 for TDM or right slot 0 for I2S, LJ.
……
1 1110 = 30dSlot 30 for TDM or right slot 14 for LJ.
1 1111 = 31dSlot 31 for TDM or right slot 15 for LJ.

Similarly, the slot assignment setting for output channel 2 to channel 8 can be done using the PASI_TX_CH2_SLOT (P0_R31) to PASI_TX_CH8_SLOT (P0_R37) registers and for input channel 1 to channel 8 by using the PASI_RX_CH1_SLOT(P0_R40) to PAS_RX_CH8_SLOT(P0_R47), respectively.

The slot word length is the same as the primary ASI channel word length set for the device. The output channel data word length must be set to the same value for all TAC5412-Q1 devices if all devices share the same ASI bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data word length configured.

The device also includes a feature that offsets the start of the slot data transfer concerning the frame sync by up to 31 cycles of the bit clock. Offset can be configured independently for input and output data paths. Table 6-4 and Table 6-5lists the programmable offset configuration settings for transmission and receive paths respectively.

Table 6-4 Programmable Offset Settings for the ASI Slot Start for transmission
P0_R28_D[4:0] : PASI_TX_OFFSET[4:0]PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START
0 0000 = 0d (default)The device follows the standard protocol timing without any offset.
0 0001 = 1dSlot start is offset by one BCLK cycle, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to standard protocol timing.
............
1 1110 = 30dSlot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
1 1111 = 31dSlot start is offset by 31 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.
Table 6-5 Programmable Offset Settings for the ASI Slot Start for Receive
P0_R38_D[4:0] : PASI_RX_OFFSET[4:0]PROGRAMMABLE OFFSET SETTING FOR SLOT DATA RECEIVE START
0 0000 = 0d (default)The device follows the standard protocol timing without any offset.
0 0001 = 1dSlot start is offset by one BCLK cycle, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to standard protocol timing.
............
1 1110 = 30dSlot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
1 1111 = 31dSlot start is offset by 31 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.

The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using the PASI_FSYNC_POL, P0_R26_D3 register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK, which can be set using the PASI_BCLK_POL, P0_R26_D2 register bit.

In addition, the word clock and bit clock can be independently configured in either Controller or Target mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC sampling frequencies.