SLASFC0 December   2023 TAD5212

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
        4. 7.3.1.4 Phase-Locked Loop (PLL) and Clock Generation
        5. 7.3.1.5 Output Channel Configurations
        6. 7.3.1.6 Reference Voltage
        7. 7.3.1.7 Programmable Microphone Bias
        8. 7.3.1.8 Signal-Chain Processing
          1. 7.3.1.8.1 DAC Signal-Chain
            1. 7.3.1.8.1.1 Programmable Channel Gain and Digital Volume Control
            2. 7.3.1.8.1.2 Programmable Channel Gain Calibration
            3. 7.3.1.8.1.3 Programmable Digital High-Pass Filter
            4. 7.3.1.8.1.4 Programmable Digital Biquad Filters
            5. 7.3.1.8.1.5 Programmable Digital Mixer
            6. 7.3.1.8.1.6 Configurable Digital Interpolation Filters
              1. 7.3.1.8.1.6.1 Linear Phase Filters
                1. 7.3.1.8.1.6.1.1 Sampling Rate: 16 kHz or 14.7 kHz
                2. 7.3.1.8.1.6.1.2 Sampling Rate: 24 kHz or 22.05 kHz
                3. 7.3.1.8.1.6.1.3 Sampling Rate: 32 kHz or 29.4 kHz
                4. 7.3.1.8.1.6.1.4 Sampling Rate: 48 kHz or 44.1 kHz
                5. 7.3.1.8.1.6.1.5 Sampling Rate: 96 kHz or 88.2 kHz
                6. 7.3.1.8.1.6.1.6 Sampling Rate: 384 kHz or 352.8 kHz
        9. 7.3.1.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 TAD5212_P0 Registers
      2. 7.5.2 TAD5212_P1 Registers
      3. 7.5.3 TAD5212_P3 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements: I2C Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see TBD for timing diagram
MINNOMMAXUNIT
STANDARD-MODE
fSCLSCL clock frequency0100kHz
tHD;STAHold time (repeated) START condition. After this period, the first clock pulse is generated.4μs
tLOWLow period of the SCL clock4.7μs
tHIGHHigh period of the SCL clock4μs
tSU;STASetup time for a repeated START condition4.7μs
tHD;DATData hold time03.45μs
tSU;DATData setup time250ns
trSDA and SCL rise time1000ns
tfSDA and SCL fall time300ns
tSU;STOSetup time for STOP condition4μs
tBUFBus free time between a STOP and START condition4.7μs
FAST-MODE
fSCLSCL clock frequency0400kHz
tHD;STAHold time (repeated) START condition. After this period, the first clock pulse is generated.0.6μs
tLOWLow period of the SCL clock1.3μs
tHIGHHigh period of the SCL clock0.6μs
tSU;STASetup time for a repeated START condition0.6μs
tHD;DATData hold time00.9μs
tSU;DATData setup time100ns
trSDA and SCL rise time20300ns
tfSDA and SCL fall time20 × (IOVDD / 5.5 V)300ns
tSU;STOSetup time for STOP condition0.6μs
tBUFBus free time between a STOP and START condition1.3μs
FAST-MODE PLUS
fSCLSCL clock frequency01000kHz
tHD;STAHold time (repeated) START condition. After this period, the first clock pulse is generated.0.26μs
tLOWLow period of the SCL clock0.5μs
tHIGHHigh period of the SCL clock0.26μs
tSU;STASetup time for a repeated START condition0.26μs
tHD;DATData hold time0μs
tSU;DATData setup time50ns
trSDA and SCL Rise Time120ns
tfSDA and SCL Fall Time20 × (IOVDD / 5.5 V)120ns
tSU;STOSetup time for STOP condition0.26μs
tBUFBus free time between a STOP and START condition0.5μs