SLASFC0
December 2023
TAD5212
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements: I2C Interface
6.7
Switching Characteristics: I2C Interface
6.8
Timing Requirements: SPI Interface
6.9
Switching Characteristics: SPI Interface
6.10
Timing Requirements: TDM, I2S or LJ Interface
6.11
Switching Characteristics: TDM, I2S or LJ Interface
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Serial Interfaces
7.3.1.1
Control Serial Interfaces
7.3.1.2
Audio Serial Interfaces
7.3.1.2.1
Time Division Multiplexed Audio (TDM) Interface
7.3.1.2.2
Inter IC Sound (I2S) Interface
7.3.1.2.3
Left-Justified (LJ) Interface
7.3.1.3
Using Multiple Devices With Shared Buses
7.3.1.4
Phase-Locked Loop (PLL) and Clock Generation
7.3.1.5
Output Channel Configurations
7.3.1.6
Reference Voltage
7.3.1.7
Programmable Microphone Bias
7.3.1.8
Signal-Chain Processing
7.3.1.8.1
DAC Signal-Chain
7.3.1.8.1.1
Programmable Channel Gain and Digital Volume Control
7.3.1.8.1.2
Programmable Channel Gain Calibration
7.3.1.8.1.3
Programmable Digital High-Pass Filter
7.3.1.8.1.4
Programmable Digital Biquad Filters
7.3.1.8.1.5
Programmable Digital Mixer
7.3.1.8.1.6
Configurable Digital Interpolation Filters
7.3.1.8.1.6.1
Linear Phase Filters
7.3.1.8.1.6.1.1
Sampling Rate: 16 kHz or 14.7 kHz
7.3.1.8.1.6.1.2
Sampling Rate: 24 kHz or 22.05 kHz
7.3.1.8.1.6.1.3
Sampling Rate: 32 kHz or 29.4 kHz
7.3.1.8.1.6.1.4
Sampling Rate: 48 kHz or 44.1 kHz
7.3.1.8.1.6.1.5
Sampling Rate: 96 kHz or 88.2 kHz
7.3.1.8.1.6.1.6
Sampling Rate: 384 kHz or 352.8 kHz
7.3.1.9
Interrupts, Status, and Digital I/O Pin Multiplexing
7.4
Device Functional Modes
7.5
Register Maps
7.5.1
TAD5212_P0 Registers
7.5.2
TAD5212_P1 Registers
7.5.3
TAD5212_P3 Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Application
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
9
Power Supply Recommendations
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
11.1
Tape and Reel Information
Package Options
Mechanical Data (Package|Pins)
RGE|24
MPQF124G
Thermal pad, mechanical data (Package|Pins)
RGE|24
QFND808
Orderable Information
slasfc0_oa
1
Features
DAC performance:
DAC to Line Out Dynamic Range:
106
dB
DAC to HP Out Dynamic Range:
102
dB
THD+N: –95 dB
Head Phone/Line Out output voltage:
Differential, 2-V
RMS
full-scale
Single-ended, 1-V
RMS
full-scale
DAC sample Rates (f
s
) = 8KHz to 768KHz
Analog Input to Output By-pass
Battery Protection
Signal Distortion Limiter
Thermal Foldback
Low Latency Filter Selection
Programmable HPF and Biquad Filters
I
2
C & SPI Control Interface
Audio Serial Interface
Format: TDM, I
2
S or Left Justified
Word Length: 16,20,24 or 32 Bits
Programmable PLL for Flexible Clocking
Low Power Modes
TBD mW for Playback
Single Supply Operation: 1.8V or 3.3V
I/O Supply Operation: 1.2V or 1.8V or 3.3V