SLASF38 December   2023 TAD5212-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
        4. 7.3.1.4 Phase-Locked Loop (PLL) and Clock Generation
        5. 7.3.1.5 Output Channel Configurations
        6. 7.3.1.6 Reference Voltage
        7. 7.3.1.7 Programmable Microphone Bias
        8. 7.3.1.8 Signal-Chain Processing
          1. 7.3.1.8.1 DAC Signal-Chain
            1. 7.3.1.8.1.1 Programmable Channel Gain and Digital Volume Control
            2. 7.3.1.8.1.2 Programmable Channel Gain Calibration
            3. 7.3.1.8.1.3 Programmable Digital High-Pass Filter
            4. 7.3.1.8.1.4 Programmable Digital Biquad Filters
            5. 7.3.1.8.1.5 Programmable Digital Mixer
            6. 7.3.1.8.1.6 Configurable Digital Interpolation Filters
              1. 7.3.1.8.1.6.1 Linear Phase Filters
                1. 7.3.1.8.1.6.1.1 Sampling Rate: 16 kHz or 14.7 kHz
                2. 7.3.1.8.1.6.1.2 Sampling Rate: 24 kHz or 22.05 kHz
                3. 7.3.1.8.1.6.1.3 Sampling Rate: 32 kHz or 29.4 kHz
                4. 7.3.1.8.1.6.1.4 Sampling Rate: 48 kHz or 44.1 kHz
                5. 7.3.1.8.1.6.1.5 Sampling Rate: 96 kHz or 88.2 kHz
                6. 7.3.1.8.1.6.1.6 Sampling Rate: 384 kHz or 352.8 kHz
        9. 7.3.1.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 TAD5212_P0 Registers
      2. 7.5.2 TAD5212_P1 Registers
      3. 7.5.3 TAD5212_P3 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.1.8.1.1 Programmable Channel Gain and Digital Volume Control

The device has an independent programmable channel gain setting for each output channel that can be set to the appropriate value based on the maximum input signal expected in the system, This can be done by configuring OUT1x_LVL_CTRL and OUT2x_LVL_CTRL bits. Coarse gain configuration from -6dB to +24dB is available with these controls in steps of 6dB. .

The device has a programmable digital volume control with a range from –100 dB to 27 dB in steps of 0.5 dB with the option to mute the channel recording. The digital volume control value can be changed dynamically while the DAC channel is powered-up and playing. During volume control changes, the soft ramp-up or ramp-down volume feature is used internally to avoid any audible artifacts. Soft-stepping can be entirely disabled using the DAC_DSP_DISABLE_SOFT_STEP (P0_R115_D1) register bit.

The digital volume control setting is independently available for each of the 4 single ended output channels. In case of 2 Channel Differential DAC, Only settings for DAC_CH1A and DAC_CH2A are applicable. The device also supports an option to gang-up the volume control setting for all channels together using the channel 1A digital volume control setting, regardless if channel 1A is powered up or powered down. This gang-up can be enabled using the DAC_DSP_DVOL_GANG (P0_R115_D0) register bit.

Table 7-12 shows the programmable options available for the digital volume control.

Table 7-12 Digital Volume Control (DVC) Programmable Settings
P0_R103_D[7:0] : DAC_CH1A_DVOL[7:0]DVC SETTING FOR OUTPUT CHANNEL 1A
0000 0000 = 0dOutput channel 1 DVC is set to mute
0000 0001 = 1dOutput channel 1 DVC is set to –100 dB
0000 0010 = 2dOutput channel 1 DVC is set to –99.5 dB
0000 0011 = 3dOutput channel 1 DVC is set to –99 dB
……
1100 1000 = 200dOutput channel 1 DVC is set to –0.5 dB
1100 1001 = 201d (default)Output channel 1 DVC is set to 0 dB
1100 1010 = 202dOutput channel 1 DVC is set to 0.5 dB
……
1111 1101 = 253dOutput channel 1 DVC is set to 26 dB
1111 1110 = 254dOutput channel 1 DVC is set to 26.5 dB
1111 1111 = 255dOutput channel 1 DVC is set to 27 dB

Similarly, the digital volume control setting for output channel 1B,2A and 2B can be configured using the CH1B_DVOL (P0_R103) to CH2B_DVOL (P0_R112) register bits, respectively.

The internal digital processing engine soft ramps up the volume from a muted level to the programmed volume level when the channel is powered up, and the internal digital processing engine soft ramps down the volume from a programmed volume to mute when the channel is powered down. This soft-stepping of volume is done to prevent abruptly powering up and powering down the playback channel which can cause audible artifacts. This feature can also be entirely disabled using the DAC_DSP_DISABLE_SOFT_STEP (P0_R115_D1) register bit.