SLASF38 December   2023 TAD5212-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
        4. 7.3.1.4 Phase-Locked Loop (PLL) and Clock Generation
        5. 7.3.1.5 Output Channel Configurations
        6. 7.3.1.6 Reference Voltage
        7. 7.3.1.7 Programmable Microphone Bias
        8. 7.3.1.8 Signal-Chain Processing
          1. 7.3.1.8.1 DAC Signal-Chain
            1. 7.3.1.8.1.1 Programmable Channel Gain and Digital Volume Control
            2. 7.3.1.8.1.2 Programmable Channel Gain Calibration
            3. 7.3.1.8.1.3 Programmable Digital High-Pass Filter
            4. 7.3.1.8.1.4 Programmable Digital Biquad Filters
            5. 7.3.1.8.1.5 Programmable Digital Mixer
            6. 7.3.1.8.1.6 Configurable Digital Interpolation Filters
              1. 7.3.1.8.1.6.1 Linear Phase Filters
                1. 7.3.1.8.1.6.1.1 Sampling Rate: 16 kHz or 14.7 kHz
                2. 7.3.1.8.1.6.1.2 Sampling Rate: 24 kHz or 22.05 kHz
                3. 7.3.1.8.1.6.1.3 Sampling Rate: 32 kHz or 29.4 kHz
                4. 7.3.1.8.1.6.1.4 Sampling Rate: 48 kHz or 44.1 kHz
                5. 7.3.1.8.1.6.1.5 Sampling Rate: 96 kHz or 88.2 kHz
                6. 7.3.1.8.1.6.1.6 Sampling Rate: 384 kHz or 352.8 kHz
        9. 7.3.1.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 TAD5212_P0 Registers
      2. 7.5.2 TAD5212_P1 Registers
      3. 7.5.3 TAD5212_P3 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM target mode and PLL on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DAC Performance for Line Output/Head Phone Playback
Full Scale Output Voltage Differential output between OUTxP and OUTxM, AVDD=3.3V 2 VRMS
Differential Output between OUTxP and OUTxM, AVDD=1.8V 1
Single-ended Output, AVDD=3.3V 1
Single-ended Output, AVDD=1.8V 0.5
Pseudo Differential Output between OUTxP and OUTxM, AVDD=3.3V 1
Pseudo Differential Output between OUTxP and OUTxM, AVDD=1.8V 0.5
SNR Signal-to-noise ratio, A-weighted(1)(2) Differential Output, 0dBFS Signal, AVDD=3.3V 119 dB
Single Ended Output, 0dBFS Signal, AVDD=3.3V 111
Pseudo Differential Output, 0dBFS Signal, AVDD=3.3V 110
Differential Output, 0dBFS Signal, AVDD=1.8V 114
Single Ended Output, 0dBFS Signal, AVDD=1.8V 105
Pseudo Differential Output, 0dBFS Signal, AVDD=1.8V 104
Differential Output, 0dBFS Signal, AVDD=3.3V, 0dBFS Signal, Power Tune Mode 112
Single Ended Output, 0dBFS Signal, AVDD=3.3V, Power Tune Mode 102
Pseudo Differential Output, 0dBFS Signal, AVDD=3.3V, Power Tune Mode 101
Differential Output, 0dBFS Signal, AVDD=1.8V, Power Tune Mode 108
Single Ended Output, 0dBFS Signal, AVDD=1.8V, Power Tune Mode 97
Pseudo Differential Output, 0dBFS Signal, AVDD=1.8V, Power Tune Mode 96
DR Dynamic range, A-weighted(2) Differential Output, -60dBFS Signal, AVDD=3.3V 119 dB
Single Ended Output, -60dBFS Signal, AVDD=3.3V 111
Pseudo Differential Output, -60dBFS Signal, AVDD=3.3V 110
Differential Output, -60dBFS Signal, AVDD=1.8V 114
Single Ended Output, -60dBFS Signal, AVDD=1.8V 105
Pseudo Differential Output, -60dBFS Signal, AVDD=1.8V 104
Differential Output, -60dBFS Signal, AVDD=3.3V, 0dBFS Signal, Power Tune Mode 112
Single Ended Output, -60dBFS Signal, AVDD=3.3V, Power Tune Mode 102
Pseudo Differential Output, -60dBFS Signal, AVDD=3.3V, Power Tune Mode 101
Differential Output, -60dBFS Signal, AVDD=1.8V, Power Tune Mode 108
Single Ended Output, -60dBFS Signal, AVDD=1.8V, Power Tune Mode 97
Pseudo Differential Output, -60dBFS Signal, AVDD=1.8V, Power Tune Mode 96
THD+N Total harmonic distortion(2) -95 dB
Head Phone Load Range 16 Ω
Line Out Load Range 600 Ω
Channel gain control range Programmable 1-dB steps –6 12 dB
Analog Bypass to Line Out/Head Phone Amplifier
Input impedance Differential input, between INxP and INxM 8.8 kΩ
Single-ended input, between INxP and INxM 4.4
Differential input, between INxP and INxM, 40k Mode 40k
Single-ended input, between INxP and INxM, 40k Mode 20k
Single Ended Full Scale Output AVDD=3.3V AVDD=3.3V 1 Vrms
Differential Full Scale Output AVDD=3.3V 2 Vrms
AVDD=1.8V 1 Vrms
Gain Error 0.1 dB
Noise, A-Weighted Idle Channel, AC Coupled Input Shorted to Ground, Fully Differential output 4.5 µVRMS
Noise, A-Weighted Idle Channel, AC Coupled Input Shorted to Ground, Single Ended output 6.3 µVRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) Idle Channel, AC Coupled Input Shorted to Ground, Fully Differential output, AVDD=3.3V 113 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) Idle Channel, AC Coupled Input Shorted to Ground, Single Ended output, AVDD=3.3V 104 dB
THD+N Total harmonic distortion(2) IN1 differential AC-coupled input selected and -1-dB full-scale AC signal input, 0-dB channel gain dB
DAC Channel OTHER PARAMETERS
Output Offset 0 Input, Fully Differential Output 0.2 mV
Output Offset 0 Input, Pseudo Differential Output 0.4 mV
Output Common Mode Common Mode Level for OUTxP and OUTxM AVDD=1.8V (Register Configurable) 0.9 V
Output Common Mode Common Mode Level for OUTxP and OUTxM AVDD=3.3V (Register Configurable) 1.66 V
Common Mode Error DC Error in Common Mode Voltage ±10 mV
Digital volume control range Programmable 0.5-dB steps –120 42 dB
Output Signal Bandwidth Upto 192KSPS FS Rate 0.46 FS
>192KSPS 100 kHz
Input data sample rate Programmable 3.675 768 kHz
Input data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3-dB point (default setting)		 2 Hz
Interchannel isolation –134 dB
Interchannel gain mismatch 0.1 dB
Interchannel phase mismatch 1-kHz sinusoidal signal 0.01 Degrees
PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 100 dB
Mute Attenuation –130 dB
Pout Output Power Delivery Single ended/Pseudo Differential RL=16 Ohms, THD+N<1% 62.5 mW
MICROPHONE BIAS
MICBIAS noise BW = 20 Hz to 20 kHz, A-weighted, 1-µF capacitor between MICBIAS and AVSS 2 µVRMS
MICBIAS voltage Bypass to AVDD AVDD V
MICBIAS voltage AVDD=1.8V 1.375 V
MICBIAS voltage AVDD=3.3V 2.75 V
DIGITAL I/O
VIL(SHDNZ) Low-level digital input logic voltage threshold SHDNZ pin –0.3 0.25 × IOVDD V
VIH(SHDNZ) High-level digital input logic voltage threshold SHDNZ pin 0.75 × IOVDD IOVDD + 0.3 V
VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8-V operation –0.3 0.35 × IOVDD V
All digital pins except SDA and SCL, IOVDD 3.3-V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8-V operation 0.65 × IOVDD IOVDD + 0.3 V
All digital pins except SDA and SCL, IOVDD 3.3-V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V
All digital pins except SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation 0.4
VOH High-level digital output voltage All digital pins except SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V
All digital pins except SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation 2.4
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 × IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 × IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3 mA, IOVDD > 2 V 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus 20
IIL Input logic-low leakage for digital inputs All digital pins, input = 0 V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode (software shutdown mode) All device external clocks stopped TBD µA
IIOVDD 1
IAVDD Current consumption with DAC to HP 2-channel operation at fS 16-kHz, MICBIAS off, PLL on, BCLK = 512 × fS TBD mA
IIOVDD 0.2
IAVDD Current consumption with DAC to HP 2-channel operation at fS 48-kHz, MICBIAS off, PLL off, BCLK = 512 × fS TBD mA
IIOVDD TBD
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.