SLASET8 December   2019 TAS2110

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PurePath™ Console 3 Software
      2. 8.3.2  Device Mode and Address Selection
      3. 8.3.3  General I2C Operation
      4. 8.3.4  Single-Byte and Multiple-Byte Transfers
      5. 8.3.5  Single-Byte Write
      6. 8.3.6  Multiple-Byte Write and Incremental Multiple-Byte Write
      7. 8.3.7  Single-Byte Read
      8. 8.3.8  Multiple-Byte Read
      9. 8.3.9  Register Organization
      10. 8.3.10 Operational Modes
        1. 8.3.10.1 Hardware Shutdown
        2. 8.3.10.2 Software Shutdown
        3. 8.3.10.3 Mute
        4. 8.3.10.4 Active
        5. 8.3.10.5 Mode Control and Software Reset
      11. 8.3.11 Faults and Status
      12. 8.3.12 Power Sequencing Requirements
      13. 8.3.13 Digital Input Pull Downs
    4. 8.4 Device Functional Modes
      1. 8.4.1 TDM Port
      2. 8.4.2 Playback Signal Path
        1. 8.4.2.1 High Pass Filter
        2. 8.4.2.2 Digital Volume Control and Amplifier Output Level
        3. 8.4.2.3 Auto-Mute During Idle Channel Mode
        4. 8.4.2.4 Auto-Start/Stop on Audio Clocks
        5. 8.4.2.5 Supply Tracking Limiters with Brown Out Prevention
        6. 8.4.2.6 Inter Chip Limiter Alignment
          1. 8.4.2.6.1 TDM Mode
        7. 8.4.2.7 Class-D Settings
      3. 8.4.3 SAR ADC
      4. 8.4.4 Boost
      5. 8.4.5 Clocks and PLL
      6. 8.4.6 Thermal Foldback
      7. 8.4.7 Internal Tone Generator
    5. 8.5 Register Maps
      1. 8.5.1   Register Summary Table Page=0x00
      2. 8.5.2   Register Summary Table Page=0x01
      3. 8.5.3   Register Summary Table Page=0x02
      4. 8.5.4   Register Summary Table Page=0x04
      5. 8.5.5   PAGE0 (page=0x00 address=0x00) [reset=0h]
        1. Table 104. Device Page Field Descriptions
      6. 8.5.6   SW_RESET (page=0x00 address=0x01) [reset=0h]
        1. Table 105. Software Reset Field Descriptions
      7. 8.5.7   PWR_CTL (page=0x00 address=0x02) [reset=Eh]
        1. Table 106. Power Control Field Descriptions
      8. 8.5.8   PB_CFG1 (page=0x00 address=0x03) [reset=20h]
        1. Table 107. Playback Configuration 1 Field Descriptions
      9. 8.5.9   MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
        1. Table 108. Misc Configuration 1 Field Descriptions
      10. 8.5.10  MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
        1. Table 109. Misc Configuration 2 Field Descriptions
      11. 8.5.11  TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
        1. Table 110. TDM Configuration 0 Field Descriptions
      12. 8.5.12  TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
        1. Table 111. TDM Configuration 1 Field Descriptions
      13. 8.5.13  TDM_CFG2 (page=0x00 address=0x08) [reset=Ah]
        1. Table 112. TDM Configuration 2 Field Descriptions
      14. 8.5.14  TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
        1. Table 113. TDM Configuration 3 Field Descriptions
      15. 8.5.15  TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
        1. Table 114. TDM Configuration 4 Field Descriptions
      16. 8.5.16  TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
        1. Table 115. TDM Configuration 7 Field Descriptions
      17. 8.5.17  TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
        1. Table 116. TDM Configuration 8 Field Descriptions
      18. 8.5.18  TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
        1. Table 117. TDM Configuration 9 Field Descriptions
      19. 8.5.19  TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
        1. Table 118. TDM Configuration 10 Field Descriptions
      20. 8.5.20  TDM_DET (page=0x00 address=0x11) [reset=7Fh]
        1. Table 119. TDM Clock detection monitor Field Descriptions
      21. 8.5.21  LIM_CFG_0 (page=0x00 address=0x12) [reset=12h]
        1. Table 120. Limiter Configuration 0 Field Descriptions
      22. 8.5.22  LIM_CFG_1 (page=0x00 address=0x13) [reset=76h]
        1. Table 121. Limiter Configuration 1 Field Descriptions
      23. 8.5.23  BOP_CFG_0 (page=0x00 address=0x14) [reset=1h]
        1. Table 122. Brown Out Prevention 0 Field Descriptions
      24. 8.5.24  BOP_CFG_1 (page=0x00 address=0x15) [reset=2Eh]
        1. Table 123. Brown Out Prevention 1 Field Descriptions
      25. 8.5.25  ICLA_CFG (page=0x00 address=0x16) [reset=60h]
        1. Table 124. ICLA gain alignment mode Field Descriptions
      26. 8.5.26  GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=Ch]
        1. Table 125. Inter Chip Limiter Alignment 0 Field Descriptions
      27. 8.5.27  ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
        1. Table 126. Inter Chip Limiter Alignment 1 Field Descriptions
      28. 8.5.28  INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
        1. Table 127. Interrupt Mask 0 Field Descriptions
      29. 8.5.29  INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
        1. Table 128. Interrupt Mask 1 Field Descriptions
      30. 8.5.30  INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
        1. Table 129. Live Interrupt Readback 0 Field Descriptions
      31. 8.5.31  INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
        1. Table 130. Live Interrupt Readback 1 Field Descriptions
      32. 8.5.32  INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
        1. Table 131. Latched Interrupt Readback 0 Field Descriptions
      33. 8.5.33  INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
        1. Table 132. Latched Interrupt Readback 1 Field Descriptions
      34. 8.5.34  VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
        1. Table 133. SAR ADC Conversion 0 Field Descriptions
      35. 8.5.35  VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
        1. Table 134. SAR ADC Conversion 1 Field Descriptions
      36. 8.5.36  TEMP (page=0x00 address=0x2C) [reset=0h]
        1. Table 135. SAR ADC Conversion 2 Field Descriptions
      37. 8.5.37  INT_CLK (page=0x00 address=0x30) [reset=19h]
        1. Table 136. Interrupt and Clock Error Field Descriptions
      38. 8.5.38  DIN_PD (page=0x00 address=0x31) [reset=40h]
        1. Table 137. Digital Input Pin Pull Down Field Descriptions
      39. 8.5.39  MISC_CFG3 (page=0x00 address=0x32) [reset=80h]
        1. Table 138. Misc Configuration 3 Field Descriptions
      40. 8.5.40  BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
        1. Table 139. Boost Configure 1 Field Descriptions
      41. 8.5.41  BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
        1. Table 140. Boost Configure 2 Field Descriptions
      42. 8.5.42  BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
        1. Table 141. Boost Configure 3 Field Descriptions
      43. 8.5.43  MISC_CFG4 (page=0x00 address=0x3D) [reset=8h]
        1. Table 142. Misc Configuration 4 Field Descriptions
      44. 8.5.44  TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
        1. Table 143. Tone Generator Field Descriptions
      45. 8.5.45  BOOST_CFG4 (page=0x00 address=0x40) [reset=36h]
        1. Table 144. Boost Configure 4 Field Descriptions
      46. 8.5.46  REV_ID (page=0x00 address=0x7D) [reset=0h]
        1. Table 145. Revision and PG ID Field Descriptions
      47. 8.5.47  I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
        1. Table 146. I2C Checksum Field Descriptions
      48. 8.5.48  BOOK (page=0x00 address=0x7F) [reset=0h]
        1. Table 147. Device Book Field Descriptions
      49. 8.5.49  PAGE1 (page=0x01 address=0x00) [reset=0h]
        1. Table 148. Device Page Field Descriptions
      50. 8.5.50  TF_CFG21 (page=0x01 address=0x08) [reset=40h]
        1. Table 149. Thermal Folder Configure Field Descriptions
      51. 8.5.51  PAGE2 (page=0x02 address=0x00) [reset=0h]
        1. Table 150. Device Page Field Descriptions
      52. 8.5.52  DVC_CFG1 (page=0x02 address=0x0C) [reset=40h]
        1. Table 151. Digital Volume Control 1 Field Descriptions
      53. 8.5.53  DVC_CFG2 (page=0x02 address=0x0D) [reset=40h]
        1. Table 152. Digital Volume Control 2 Field Descriptions
      54. 8.5.54  DVC_CFG3 (page=0x02 address=0x0E) [reset=0h]
        1. Table 153. Digital Volume Control 3 Field Descriptions
      55. 8.5.55  DVC_CFG4 (page=0x02 address=0x0F) [reset=0h]
        1. Table 154. Digital Volume Control 4 Field Descriptions
      56. 8.5.56  DVC_CFG5 (page=0x02 address=0x10) [reset=3h]
        1. Table 155. Digital Volume Control 5 Field Descriptions
      57. 8.5.57  DVC_CFG6 (page=0x02 address=0x11) [reset=4Ah]
        1. Table 156. Digital Volume Control 6 Field Descriptions
      58. 8.5.58  DVC_CFG7 (page=0x02 address=0x12) [reset=51h]
        1. Table 157. Digital Volume Control 7 Field Descriptions
      59. 8.5.59  DVC_CFG7 (page=0x02 address=0x13) [reset=6Ch]
        1. Table 158. Digital Volume Control 8 Field Descriptions
      60. 8.5.60  LIM_CFG1 (page=0x02 address=0x14) [reset=2Dh]
        1. Table 159. Limiter Configuration 1 Field Descriptions
      61. 8.5.61  LIM_CFG2 (page=0x02 address=0x15) [reset=6Ah]
        1. Table 160. Limiter Configuration 2- Sets limiter max attenuation Field Descriptions
      62. 8.5.62  LIM_CFG3 (page=0x02 address=0x16) [reset=86h]
        1. Table 161. Limiter Configuration 3- Sets limiter max attenuation Field Descriptions
      63. 8.5.63  LIM_CFG4 (page=0x02 address=0x17) [reset=6Fh]
        1. Table 162. Limiter Configuration 4- Sets limiter max attenuation Field Descriptions
      64. 8.5.64  LIM_CFG5 (page=0x02 address=0x18) [reset=47h]
        1. Table 163. Limiter Configuration 5 Field Descriptions
      65. 8.5.65  LIM_CFG6 (page=0x02 address=0x19) [reset=5Ch]
        1. Table 164. Limiter Configuration 6 Field Descriptions
      66. 8.5.66  LIM_CFG7 (page=0x02 address=0x1A) [reset=28h]
        1. Table 165. Limiter Configuration 7 Field Descriptions
      67. 8.5.67  LIM_CFG8 (page=0x02 address=0x1B) [reset=F6h]
        1. Table 166. Limiter Configuration 8 Field Descriptions
      68. 8.5.68  LIM_CFG9 (page=0x02 address=0x1C) [reset=16h]
        1. Table 167. Limiter Configuration 9 Field Descriptions
      69. 8.5.69  LIM_CFG10 (page=0x02 address=0x1D) [reset=66h]
        1. Table 168. Limiter Configuration 10 Field Descriptions
      70. 8.5.70  LIM_CFG11 (page=0x02 address=0x1E) [reset=66h]
        1. Table 169. Limiter Configuration 11 Field Descriptions
      71. 8.5.71  LIM_CFG12 (page=0x02 address=0x1F) [reset=66h]
        1. Table 170. Limiter Configuration 12 Field Descriptions
      72. 8.5.72  LIM_CFG13 (page=0x02 address=0x20) [reset=34h]
        1. Table 171. Limiter Configuration 13 Field Descriptions
      73. 8.5.73  LIM_CFG14 (page=0x02 address=0x21) [reset=CCh]
        1. Table 172. Limiter Configuration 14 Field Descriptions
      74. 8.5.74  LIM_CFG15 (page=0x02 address=0x22) [reset=CCh]
        1. Table 173. Limiter Configuration 15 Field Descriptions
      75. 8.5.75  LIM_CFG16 (page=0x02 address=0x23) [reset=CDh]
        1. Table 174. Limiter Configuration 16 Field Descriptions
      76. 8.5.76  LIM_CFG17 (page=0x02 address=0x24) [reset=10h]
        1. Table 175. Limiter Configuration 1 Field Descriptions
      77. 8.5.77  LIM_CFG18 (page=0x02 address=0x25) [reset=0h]
        1. Table 176. Limiter Configuration 2 Field Descriptions
      78. 8.5.78  LIM_CFG19 (page=0x02 address=0x26) [reset=0h]
        1. Table 177. Limiter Configuration 3 Field Descriptions
      79. 8.5.79  LIM_CFG20 (page=0x02 address=0x27) [reset=0h]
        1. Table 178. Limiter Configuration 4 Field Descriptions
      80. 8.5.80  BOP_CFG1 (page=0x02 address=0x28) [reset=2Eh]
        1. Table 179. Brown Out Prevention 1 Field Descriptions
      81. 8.5.81  BOP_CFG2 (page=0x02 address=0x29) [reset=66h]
        1. Table 180. Brown Out Prevention 2 Field Descriptions
      82. 8.5.82  BOP_CFG3 (page=0x02 address=0x2A) [reset=66h]
        1. Table 181. Brown Out Prevention 3 Field Descriptions
      83. 8.5.83  BOP_CFG4 (page=0x02 address=0x2B) [reset=66h]
        1. Table 182. Brown Out Prevention 4 Field Descriptions
      84. 8.5.84  BOP_CFG5 (page=0x02 address=0x2C) [reset=2Bh]
        1. Table 183. Brown Out Prevention 5 Field Descriptions
      85. 8.5.85  BOP_CFG6 (page=0x02 address=0x2D) [reset=33h]
        1. Table 184. Brown Out Prevention 6 Field Descriptions
      86. 8.5.86  BOP_CFG7 (page=0x02 address=0x2E) [reset=33h]
        1. Table 185. Brown Out Prevention 7 Field Descriptions
      87. 8.5.87  BOP_CFG8 (page=0x02 address=0x2F) [reset=33h]
        1. Table 186. Brown Out Prevention 8 Field Descriptions
      88. 8.5.88  HPFC_CFG1 (page=0x02 address=0x30) [reset=7Fh]
        1. Table 187. HPF Coefficient 1 Field Descriptions
      89. 8.5.89  HPFC_CFG2 (page=0x02 address=0x31) [reset=FBh]
        1. Table 188. HPF Coefficient 2 Field Descriptions
      90. 8.5.90  HPFC_CFG3 (page=0x02 address=0x32) [reset=B6h]
        1. Table 189. HPF Coefficient 3 Field Descriptions
      91. 8.5.91  HPFC_CFG4 (page=0x02 address=0x33) [reset=14h]
        1. Table 190. HPF Coefficient 4 Field Descriptions
      92. 8.5.92  HPFC_CFG5 (page=0x02 address=0x34) [reset=80h]
        1. Table 191. HPF Coefficient 5 Field Descriptions
      93. 8.5.93  HPFC_CFG6 (page=0x02 address=0x35) [reset=4h]
        1. Table 192. HPF Coefficient 6 Field Descriptions
      94. 8.5.94  HPFC_CFG7 (page=0x02 address=0x36) [reset=49h]
        1. Table 193. HPF Coefficient 7 Field Descriptions
      95. 8.5.95  HPFC_CFG8 (page=0x02 address=0x37) [reset=ECh]
        1. Table 194. HPF Coefficient 8 Field Descriptions
      96. 8.5.96  HPFC_CFG9 (page=0x02 address=0x38) [reset=7Fh]
        1. Table 195. HPF Coefficient 9 Field Descriptions
      97. 8.5.97  HPFC_CFG10 (page=0x02 address=0x39) [reset=7Fh]
        1. Table 196. HPF Coefficient 10 Field Descriptions
      98. 8.5.98  HPFC_CFG11 (page=0x02 address=0x3A) [reset=6Ch]
        1. Table 197. HPF Coefficient 11 Field Descriptions
      99. 8.5.99  HPFC_CFG12 (page=0x02 address=0x3B) [reset=28h]
        1. Table 198. HPF Coefficient 12 Field Descriptions
      100. 8.5.100 TG_CFG1 (page=0x02 address=0x3C) [reset=3Fh]
        1. Table 199. Tone Generator 1 Freq Calc 1 Field Descriptions
      101. 8.5.101 TG_CFG2 (page=0x02 address=0x3D) [reset=FFh]
        1. Table 200. Tone Generator 1 Freq Calc 1 Field Descriptions
      102. 8.5.102 TG_CFG3 (page=0x02 address=0x3E) [reset=7Ah]
        1. Table 201. Tone Generator 1 Freq Calc 1 Field Descriptions
      103. 8.5.103 TG_CFG4 (page=0x02 address=0x3F) [reset=E3h]
        1. Table 202. Tone Generator 1 Freq Calc 1 Field Descriptions
      104. 8.5.104 TG_CFG5 (page=0x02 address=0x40) [reset=1h]
        1. Table 203. Tone Generator 1 Freq Calc 2 Field Descriptions
      105. 8.5.105 TG_CFG6 (page=0x02 address=0x41) [reset=1h]
        1. Table 204. Tone Generator 1 Freq Calc 2 Field Descriptions
      106. 8.5.106 TG_CFG7 (page=0x02 address=0x42) [reset=5Bh]
        1. Table 205. Tone Generator 1 Freq Calc 2 Field Descriptions
      107. 8.5.107 TG_CFG8 (page=0x02 address=0x43) [reset=4Ch]
        1. Table 206. Tone Generator 1 Freq Calc 2 Field Descriptions
      108. 8.5.108 TG_CFG9 (page=0x02 address=0x44) [reset=0h]
        1. Table 207. Tone Generator 1 Freq Calc 3 Field Descriptions
      109. 8.5.109 TG_CFG10 (page=0x02 address=0x45) [reset=0h]
        1. Table 208. Tone Generator 1 Freq Calc 3 Field Descriptions
      110. 8.5.110 TG_CFG11 (page=0x02 address=0x46) [reset=3h]
        1. Table 209. Tone Generator 1 Freq Calc 3 Field Descriptions
      111. 8.5.111 TG_CFG12 (page=0x02 address=0x47) [reset=1Fh]
        1. Table 210. Tone Generator 1 Freq Calc 3 Field Descriptions
      112. 8.5.112 TG_CFG13 (page=0x02 address=0x48) [reset=2h]
        1. Table 211. Tone Generator 1 Amplitude Calc Field Descriptions
      113. 8.5.113 TG_CFG14 (page=0x02 address=0x49) [reset=46h]
        1. Table 212. Tone Generator 1 Amplitude Calc Field Descriptions
      114. 8.5.114 TG_CFG15 (page=0x02 address=0x4A) [reset=B4h]
        1. Table 213. Tone Generator 1 Amplitude Calc Field Descriptions
      115. 8.5.115 TG_CFG16 (page=0x02 address=0x4B) [reset=E4h]
        1. Table 214. Tone Generator 1 Amplitude Calc Field Descriptions
      116. 8.5.116 TG_CFG17 (page=0x02 address=0x4C) [reset=E0h]
        1. Table 215. Tone Generator 2 Freq Calc 1 Field Descriptions
      117. 8.5.117 TG_CFG18 (page=0x02 address=0x4D) [reset=0h]
        1. Table 216. Tone Generator 2 Freq Calc 1 Field Descriptions
      118. 8.5.118 TG_CFG19 (page=0x02 address=0x4E) [reset=0h]
        1. Table 217. Tone Generator 2 Freq Calc 1 Field Descriptions
      119. 8.5.119 TG_CFG20 (page=0x02 address=0x4F) [reset=0h]
        1. Table 218. Tone Generator 2 Freq Calc 1 Field Descriptions
      120. 8.5.120 TG_CFG21 (page=0x02 address=0x50) [reset=6Eh]
        1. Table 219. Tone Generator 2 Freq Calc 2 Field Descriptions
      121. 8.5.121 TG_CFG22 (page=0x02 address=0x51) [reset=D9h]
        1. Table 220. Tone Generator 2 Freq Calc 2 Field Descriptions
      122. 8.5.122 TG_CFG23 (page=0x02 address=0x52) [reset=EBh]
        1. Table 221. Tone Generator 2 Freq Calc 2 Field Descriptions
      123. 8.5.123 TG_CFG24 (page=0x02 address=0x53) [reset=A1h]
        1. Table 222. Tone Generator 2 Freq Calc 2 Field Descriptions
      124. 8.5.124 TG_CFG25 (page=0x02 address=0x54) [reset=0h]
        1. Table 223. Tone Generator 2 Freq Calc 3 Field Descriptions
      125. 8.5.125 TG_CFG26 (page=0x02 address=0x55) [reset=0h]
        1. Table 224. Tone Generator 2 Freq Calc 3 Field Descriptions
      126. 8.5.126 TG_CFG27 (page=0x02 address=0x56) [reset=0h]
        1. Table 225. Tone Generator 2 Freq Calc 3 Field Descriptions
      127. 8.5.127 TG_CFG28 (page=0x02 address=0x57) [reset=2Ch]
        1. Table 226. Tone Generator 2 Freq Calc 3 Field Descriptions
      128. 8.5.128 TG_CFG29 (page=0x02 address=0x58) [reset=8h]
        1. Table 227. Tone Generator 2 Amplitude Calc Field Descriptions
      129. 8.5.129 TG_CFG30 (page=0x02 address=0x59) [reset=9h]
        1. Table 228. Tone Generator 2 Amplitude Calc Field Descriptions
      130. 8.5.130 TG_CFG31 (page=0x02 address=0x5A) [reset=BCh]
        1. Table 229. Tone Generator 2 Amplitude Calc Field Descriptions
      131. 8.5.131 TG_CFG32 (page=0x02 address=0x5B) [reset=C4h]
        1. Table 230. Tone Generator 2 Amplitude Calc Field Descriptions
      132. 8.5.132 LD_CFG0 (page=0x02 address=0x5C) [reset=64h]
        1. Table 231. Load Diagnostics Resistance Upper Threshold Field Descriptions
      133. 8.5.133 LD_CFG1 (page=0x02 address=0x5D) [reset=0h]
        1. Table 232. Load Diagnostics Resistance Upper Threshold Field Descriptions
      134. 8.5.134 LD_CFG2 (page=0x02 address=0x5E) [reset=0h]
        1. Table 233. Load Diagnostics Resistance Upper Threshold Field Descriptions
      135. 8.5.135 LD_CFG3 (page=0x02 address=0x5F) [reset=0h]
        1. Table 234. Load Diagnostics Resistance Upper Threshold Field Descriptions
      136. 8.5.136 LD_CFG4 (page=0x02 address=0x60) [reset=0h]
        1. Table 235. Load Diagnostics Resistance Lower Threshold Field Descriptions
      137. 8.5.137 LD_CFG5 (page=0x02 address=0x61) [reset=80h]
        1. Table 236. Load Diagnostics Resistance Lower Threshold Field Descriptions
      138. 8.5.138 LD_CFG6 (page=0x02 address=0x62) [reset=0h]
        1. Table 237. Load Diagnostics Resistance Lower Threshold Field Descriptions
      139. 8.5.139 LD_CFG7 (page=0x02 address=0x63) [reset=0h]
        1. Table 238. Load Diagnostics Resistance Lower Threshold Field Descriptions
      140. 8.5.140 IDC_CFG0 (page=0x02 address=0x64) [reset=0h]
        1. Table 239. Idle channel detection threshold Field Descriptions
      141. 8.5.141 IDC_CFG1 (page=0x02 address=0x65) [reset=20h]
        1. Table 240. Idle channel detection threshold Field Descriptions
      142. 8.5.142 IDC_CFG2 (page=0x02 address=0x66) [reset=C4h]
        1. Table 241. Idle channel detection threshold Field Descriptions
      143. 8.5.143 IDC_CFG3 (page=0x02 address=0x67) [reset=9Ch]
        1. Table 242. Idle channel detection threshold Field Descriptions
      144. 8.5.144 IDC_CFG7 (page=0x02 address=0x6C) [reset=0h]
        1. Table 243. Hystersis for idle channel detection Field Descriptions
      145. 8.5.145 IDC_CFG8 (page=0x02 address=0x6D) [reset=0h]
        1. Table 244. Hystersis for idle channel detection Field Descriptions
      146. 8.5.146 IDC_CFG9 (page=0x02 address=0x6E) [reset=12h]
        1. Table 245. Hystersis for idle channel detection Field Descriptions
      147. 8.5.147 IDC_CFG10 (page=0x02 address=0x6F) [reset=C0h]
        1. Table 246. Hystersis for idle channel detection Field Descriptions
      148. 8.5.148 TF_CFG_1 (page=0x02 address=0x7C) [reset=72h]
        1. Table 247. Thermal foldback limiter slope (in db/C) Field Descriptions
      149. 8.5.149 TF_CFG_2 (page=0x02 address=0x7D) [reset=14h]
        1. Table 248. Thermal foldback limiter slope (in db/C) Field Descriptions
      150. 8.5.150 TF_CFG_3 (page=0x02 address=0x7E) [reset=82h]
        1. Table 249. Thermal foldback limiter slope (in db/C) Field Descriptions
      151. 8.5.151 TF_CFG_4 (page=0x02 address=0x7F) [reset=C0h]
        1. Table 250. Thermal foldback limiter slope (in db/C) Field Descriptions
      152. 8.5.152 PAGE4 (page=0x04 address=0x00) [reset=0h]
        1. Table 251. Device Page Field Descriptions
      153. 8.5.153 LD_CFG8 (page=0x04 address=0x18) [reset=0h]
        1. Table 252. Load Resistance Value after load diagnostics is completed Field Descriptions
      154. 8.5.154 LD_CFG9 (page=0x04 address=0x19) [reset=0h]
        1. Table 253. Load Resistance Value after load diagnostics is completed Field Descriptions
      155. 8.5.155 LD_CFG10 (page=0x04 address=0x1A) [reset=0h]
        1. Table 254. Load Resistance Value after load diagnostics is completed Field Descriptions
      156. 8.5.156 LD_CFG11 (page=0x04 address=0x1B) [reset=0h]
        1. Table 255. Load Resistance Value after load diagnostics is completed Field Descriptions
      157. 8.5.157 TF_CFG4 (page=0x04 address=0x58) [reset=0h]
        1. Table 256. Thermal foldback hold count (samples) Field Descriptions
      158. 8.5.158 TF_CFG5 (page=0x04 address=0x59) [reset=0h]
        1. Table 257. Thermal foldback hold count (samples) Field Descriptions
      159. 8.5.159 TF_CFG6 (page=0x04 address=0x5A) [reset=0h]
        1. Table 258. Thermal foldback hold count (samples) Field Descriptions
      160. 8.5.160 TF_CFG7 (page=0x04 address=0x5B) [reset=64h]
        1. Table 259. Thermal foldback hold count (samples) Field Descriptions
      161. 8.5.161 TF_CFG8 (page=0x04 address=0x5C) [reset=40h]
        1. Table 260. Thermal foldback limiter release rate (db/samples) Field Descriptions
      162. 8.5.162 TF_CFG9 (page=0x04 address=0x5D) [reset=BDh]
        1. Table 261. Thermal foldback limiter release rate (db/samples) Field Descriptions
      163. 8.5.163 TF_CFG10 (page=0x04 address=0x5E) [reset=B7h]
        1. Table 262. Thermal foldback limiter release rate (db/samples) Field Descriptions
      164. 8.5.164 TF_CFG11 (page=0x04 address=0x5F) [reset=B0h]
        1. Table 263. Thermal foldback limiter release rate (db/samples) Field Descriptions
      165. 8.5.165 TF_CFG12 (page=0x04 address=0x60) [reset=39h]
        1. Table 264. Thermal foldback limiter temperature threshold Field Descriptions
      166. 8.5.166 TF_CFG13 (page=0x04 address=0x61) [reset=82h]
        1. Table 265. Thermal foldback limiter temperature threshold Field Descriptions
      167. 8.5.167 TF_CFG14 (page=0x04 address=0x62) [reset=60h]
        1. Table 266. Thermal foldback limiter temperature threshold Field Descriptions
      168. 8.5.168 TF_CFG16 (page=0x04 address=0x63) [reset=7Fh]
        1. Table 267. Thermal foldback limiter temperature threshold Field Descriptions
      169. 8.5.169 TF_CFG17 (page=0x04 address=0x64) [reset=2Dh]
        1. Table 268. Thermal foldback max gain reduction (dB) Field Descriptions
      170. 8.5.170 TF_CFG18 (page=0x04 address=0x65) [reset=6Ah]
        1. Table 269. Thermal foldback max gain reduction (dB) Field Descriptions
      171. 8.5.171 TF_CFG19 (page=0x04 address=0x66) [reset=86h]
        1. Table 270. Thermal foldback max gain reduction (dB) Field Descriptions
      172. 8.5.172 TF_CFG20 (page=0x04 address=0x67) [reset=6Fh]
        1. Table 271. Thermal foldback max gain reduction (dB) Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Mono/Stereo Configuration
        2. 9.2.2.2 Boost Converter Passive Devices
        3. 9.2.2.3 EMI Passive Devices
        4. 9.2.2.4 Miscellaneous Passive Devices
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
    2. 10.2 Power Supply Sequencing
      1. 10.2.1 Boost Supply Details
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TA = 25 °C, VBAT = 3.6 V, (External PVDD = 12 V), VDD = 1.8 V, RL = 8Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 16 dBV (External PVDD Gain=18 dBV), SDZ = 1, Thermal Foldback Disabled, Measured filter free with an Audio Precision with a 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT
and OUTPUT
VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL 0.65 × VDD V
VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL 0.35 × VDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 × VDD V
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL 0.3 × VDD V
VOH High-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOH = 2 mA. VDD – 0.45 V V
VOL Low-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOL = –2 mA. 0.45 V
VOL(I2C) Low-level digital output voltage SDA and SCL; IOL(I2C) = –2 mA. 0.2 × VDD V
VOL(IRQZ) Low-level digital output voltage for IRQZ open drain Output IRQZ; IOL(IRQZ) = –2 mA. 0.45 V
IIH Input logic-high leakage for digital inputs All digital pins; Input = VDD. –5 0.1 5 µA
IIL Input logic-low leakage for digital inputs All digital pins; Input = GND. –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pull down resistance for digital input/IO pins when asserted on SDOUT, SDIN, FSYNC, SBCLK 50 kΩ
AMPLIFIER PERFORMANCE - Internal Boost
Output Voltage for Full-scale digital Input Measured at -6 dB FS input 6.32 Vrms
POUT Maximum Continuous Output Power RL = 32Ω + 33 µH, THD+N = 0.03 %, fin = 1 kHz 1.25 W
RL = 8 Ω + 33 µH, THD+N = 0.03 %, fin = 1 kHz 5 W
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz 6.1 W
System efficiency at POUT = 1 W RL = 8 Ω + 33 µH, fin = 1 kHz 82.5 %
RL = 4 Ω + 33 µH, fin = 1 kHz 79.5 %
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V 83 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V 85.2 %
System efficiency at POUT =0.5 W RL = 8 Ω + 33 µH, fin = 1 kHz 75.8 %
RL = 4 Ω + 33 µH, fin = 1 kHz 80.3 %
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V 84.9 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V 80.5 %
System efficiency at 0.1% THD+N power level RL = 32 Ω + 33 µH, fin = 1 kHz, 79.1 %
RL = 8 Ω + 33 µH, fin = 1 kHz, 81.2 %
RL = 4 Ω + 33 µH, fin = 1 kHz 75.7 %
THD+N Total harmonic distortion + noise POUT = 0.25 W, RL = 32Ω + 33 µH, fin = 1 kHz 0.01 %
POUT = 1 W, RL = 8 Ω + 33 µH, fin = 1 kHz 0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 1 kHz 0.01 %
VN Idle channel noise A-Weighted, 20 Hz - 20 kHz, DAC Modulator Running 14.8 µV
FPWM Class-D PWM switching frequency Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz 352.8 kHz
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz 384 kHz
VOS Output offset voltage -1 1 mV
DNR Dynamic range A-Weighted, -60 dBFS Method 106.5 dB
SNR Signal to noise ratio A-Weighted, Referenced to 1 % THD+N Output Level 112.5 dB
KCP Click and pop performance Into and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. Measured with APx Plugin. 4 mV
Programmable output level range 8 18 dBV
Programmable output level step size 0.5 dB
AVERROR Amplifier gain error POUT = 1 W ±0.1 dB
Mute attenuation Device in Shutdown or Muted in Normal Operation 110 dB
VBAT power-supply rejection ratio VBAT = 3.6 V + 200 mVpp, fripple = 217 Hz 108 dB
VBAT = 3.6 V + 200 mVpp, fripple = 20 kHz 87.5 dB
AVDD power-supply rejection ratio VDD = 1.8 V + 200 mVpp, fripple = 217 Hz 98 dB
VDD = 1.8 V + 200 mVpp, fripple = 20 kHz 89 dB
Turn on time from release of SW shutdown No Volume Ramping 1.8 ms
Volume Ramping 4.5 ms
Turn off time from assertion of SW shutdown to amp Hi-Z No Volume Ramping 0.9 ms
Volume Ramping 12.5 ms
AMPLIFIER PERFORMANCE - External PVDD
Output Voltage for Full-scale digital Input Measured at -6 dB FS input 7.94 Vrms
POUT Maximum Continuous Output Power RL = 32Ω + 33 µH, THD+N = 1 %, fin = 1 kHz 1.3 W
RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz 5.2 W
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz 10.4 W
RL = 32Ω + 33 µH, THD+N = 10 %, fin = 1 kHz 1.6 W
RL = 8 Ω + 33 µH, THD+N = 10 %, fin = 1 kHz 6.3 W
RL = 4 Ω + 33 µH, THD+N = 10%, fin = 1 kHz 12.6 W
System efficiency at POUT = 1 W RL = 8 Ω + 33 µH, fin = 1 kHz 85.8 %
RL = 4 Ω + 33 µH, fin = 1 kHz 81.8 %
RL = 8 Ω + 33 µH, fin = 1 kHz, External PVDD = 8.4 V 87.9 %
RL = 4 Ω + 33 µH, fin = 1 kHz,  External PVDD = 8.4 V 83.8 %
System efficiency at 0.1% THD+N power level RL = 32 Ω + 33 µH, fin = 1 kHz, 89.4 %
RL = 8 Ω + 33 µH, fin = 1 kHz, 91.2 %
RL = 4 Ω + 33 µH, fin = 1 kHz 87.2 %
RL = 32 Ω + 33 µH, fin = 1 kHz, External PVDD = 8.4 V 83.9 %
RL = 8 Ω + 33 µH, fin = 1 kHz, External PVDD = 8.4 V 91.9 %
RL = 4 Ω + 33 µH, fin = 1 kHz, External PVDD = 8.4 V 88 %
THD+N Total harmonic distortion + noise POUT = 0.25 W, RL = 32Ω + 33 µH, fin = 1 kHz 0.01 %
POUT = 1 W, RL = 8 Ω + 33 µH, fin = 1 kHz 0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 1 kHz 0.02 %
VN Idle channel noise A-Weighted, 20 Hz - 20 kHz, DAC Modulator Running 21.3 µV
FPWM Class-D PWM switching frequency Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz 352.8 kHz
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz 384 kHz
VOS Output offset voltage -1 1 mV
DNR Dynamic range A-Weighted, -60 dBFS Method 109 dB
SNR Signal to noise ratio A-Weighted, Referenced to 1 % THD+N Output Level 109.5 dB
KCP Click and pop performance Into and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. Measured with APx Plugin. 3 mV
Programmable output level range 8 18 dBV
Programmable output level step size 0.5 dB
AVERROR Amplifier gain error POUT = 1 W ±0.1 dB
Mute attenuation Device in Shutdown or Muted in Normal Operation 110 dB
VBAT power-supply rejection ratio VBAT = 3.6 V + 200 mVpp, fripple = 217 Hz 110 dB
VBAT = 3.6 V + 200 mVpp, fripple = 20 kHz 90 dB
PVDD power-supply rejection ratio PVDD = 12 V + 200 mVpp, fripple = 217 Hz 105 dB
PVDD = 12 V + 200 mVpp, fripple = 20 kHz 90 dB
AVDD power-supply rejection ratio VDD = 1.8 V + 200 mVpp, fripple = 217 Hz 86 dB
VDD = 1.8 V + 200 mVpp, fripple = 20 kHz 73 dB
Turn on time from release of SW shutdown No Volume Ramping 1.8 ms
Volume Ramping 4.5 ms
Turn off time from assertion of SW shutdown to amp Hi-Z No Volume Ramping 0.75 ms
Volume Ramping 12.5 ms
BOOST
CONVERTER
Max Output Voltage 0.1A DC load, Average voltage (w/o including ripple) 11 V
Startup inrush current limit Class-G Mode 1 A
Startup inrush limit time Class-G Mode 0.45 ms
Switching Frequency PFM mode 50 kHz
Current Control Mode 4 MHz
Inductor Peak Current Limit default setting 4 A
DIE TEMPERATURE
SENSOR
Resolution 8 bits
Die temperature measurement range -40 150 °C
Die temperature resolution 1 °C
Die temperature accuracy ±5 °C
VOLTAGE
MONITOR
Resolution 10 bits
VBAT measurement range 2 6 V
VBAT resolution 15.6 mV
VBAT accuracy ±25 mV
TDM SERIAL AUDIO
PORT
PCM Sample Rates & FSYNC Input Frequency 7.35 192 kHz
SBCLK Input Frequency I2S/TDM Operation 0.4704 24.576 MHz
SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation 1 ns
RMS Jitter above 40 kHz that can be tolerated without performance degradation 10 ns
SBCLK Cycles per FSYNC in I2S and TDM Modes Values: 64, 96, 128, 192, 256, 384 and 512 64 512 Cycles
PCM PLAYBACK
CHARACTERISTICS to fs ≤ 48 kHz
fs Sample Rates 7.35 48 kHz
Passband LPF Corner 0.454 fs
Passband Ripple 20 Hz to LPF cutoff -0.3 0.3 dB
Stop Band Attenuation ≥ 0.55 fs 60 dB
≥ 1 fs 65 dB
Group Delay DC to 0.454 fs 8.6 1/fs
PCM PLAYBACK
CHARACTERISTICS fs > 48 kHz
fs Sample Rates 88.2 192 kHz
Passband LPF Corner fs = 96 kHz 0.42 fs
fs = 192 kHz 0.21 fs
Passband Ripple DC to LPF cutoff -0.5 0.5 dB
Stop Band Attenuation ≥ 0.55 fs 60 dB
≥ 1 fs 65 dB
Group Delay DC to 0.375 fs for 96 kHz 8.6 1/fs
TYPICAL CURRENT
CONSUMPTION
Current consumption in hardware shutdown SDZ = 0, VBAT 0.1 µA
SDZ = 0, VDD 1 µA
Current consumption in software shutdown All Clocks Stopped, VBAT 0.5 µA
All Clocks Stopped, VDD 10 µA
Current consumption in idle channel Clocking 0s PCM mode, VBAT 2.7 mA
Clocking 0s PCM mode, VDD 7.9 mA
Current consumption during active operation fs = 48 kHz, VBAT 4.6 mA
fs = 48 kHz, VDD 7.9 mA
PROTECTION
CIRCUITRY
Thermal shutdown temperature 140 °C
Thermal shutdown retry 1.5 s
VBAT undervoltage lockout threshold (UVLO) UVLO is asserted 2 V
UVLO is released 2.55 V
Output short circuit limit Output to Output, Output to GND, Output to VBST or Output to VBAT Short 3.75 A