SLASET8 Data sheet

SLASET8 December 2019 TAS2110

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RPP|32
- MPQF543A

Thermal pad, mechanical data (Package|Pins)

RPP|32
- QFND626

Orderable Information

8.3.11 Faults and Status

During the power-up sequence, the power-on-reset circuit (POR) monitoring the VDD and VBAT pins will hold the device in reset (including all configuration registers) until the supply is valid. The device will not exit hardware shutdown until VDD and VBAT are valid and the SDZ pin is released. Once SDZ is released, the digital core voltage regulator will power up, enabling detection of the operational mode. If VDD dips below the POR threshold, the device will immediately be forced into a reset state.

The device also monitors the VBAT supply and holds the analog core in power down if the supply is below the UVLO threshold. If the TAS2110 is in active operation and a UVLO fault occurs, the analog supplies will immediately power down to protect the device. These faults are latching and require a transition through HW/SW shutdown to clear the fault. The live and latched registers will report UVLO faults.

The device transitions into software shutdown mode if it detects any faults with the TDM clocks such as:

• Invalid SBCLK to FSYNC ratio

• Invalid FSYNC frequency

• Halting of SBCLK or FSYNC clocks

Upon detection of a TDM clock error, the device transitions into software shutdown mode as quickly as possible to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back to its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt mask register bit is set low (INT_MASK[2]). The clock fault is also available for readback in the live or latched fault status registers (INT_LIVE[2] and INT_LTCH[2]). Reading the latched fault status register (INT_LTCH[7:0]) clears the register.

The TAS2110 also monitors die temperature and Class-D load current and will enter software shutdown mode if either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if the appropriate fault interrupt mask register bit is set low (INT_MASK[0] for over temp and INT_MASK[1] for over current). The fault status can also be monitored in the live and latched fault registers as with the TDM clock error.

Die over temp and Class-D over current errors can either be latching (for example the device will enter software shutdown until a HW/SW shutdown sequence is applied) or they can be configured to automatically retry after a prescribed time. This behavior can be configured in the OTE_RETRY and OCE_RETRY register bits (for over temp and over current respectively). Even in latched mode, the Class-D will not attempt to retry after an over temp or over current error until the retry time period (1.5 s) has elapsed. This prevents applying repeated stress to the device in a rapid fashion that could lead to device damage. If the device has been cycled through SW/HW shutdown, the device will only begin to operate after the retry time period.

The status registers (and IRQZ pin if enabled via the status mask register) also indicates limiter behavior including when the limiter is activity, when VBAT is below the inflection point, when maximum attenuation has been applied, when the limiter is in infinite hold and when the limiter has muted the audio.

Interrupts can be queried using the INT_LIVE[9:0] and INT_LTCH[13:0] registers and correspond to the INT_MASK[10:0] Interrupts. The latched registers are cleared by writing the self clearing register INT_CLR_LTCH high.

The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be pulled up with a resistor to . An internal pull up resistor is provided in the TAS2110 and can be accessed by setting the IRQZ_PU register bit high. Figure 38 below highlights the IRQZ pin circuit.

Figure 38. IRQZ Pin

Table 8. Fault Interrupt Mask

INT_MASK[10:0] BIT	INTERRUPT	DEFAULT (1 = Mask)
0	Over Temp Error	`0`
1	Over Current Error	`0`
2	TDM Clock Error	`1`
3	Limiter Active	`1`
4	Limter Voltage < Inf Point	`1`
5	Limiter Max Atten	`1`
6	Limiter Inf Hold	`1`
7	Limiter Mute	`1`
8	Brown Out on VBAT Supply	`0`
9	Brown Out Protection Active	`1`
10	Brown Out Power Down (Latched Only)	`1`

Table 9. IRQ Clear Latched

INT_CLR_LTCH	STATE
`0`	Don't Clear
`1`	Clear (self clearing)

Table 10. IRQZ Internal Pull Up Enable

IRQZ_PU	STATE
`0`	Disabled (default)
`1`	Enabled

Table 11. IRQZ Polarity

IRQZ_POL	STATE
`0`	Active High
`1`	Active Low (default)

Table 12. IRQZ Assert Interrupt Configuration

IRQZ_PIN_CFG[1:0]	VALUE
`00`	On any unmasked live interrupts
`01`	On any unmasked latched interrupts (default)
`10`	For 2-4 ms one time on any unmasked live interrupt event
`11`	For 2-4 ms every 4 ms on any unmasked latched interrupts

Table 13. Retry after Over Current Event

OCE_RETRY	STATE
`0`	Disabled (default)
`1`	Enabled

Table 14. Retry after Over Temperature Event

OTE_RETRY	VALUE
`0`	Do not retry (default)
`1`	Retry after 1.5 s