SLASFC6 August   2024 TAS2120

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Boost
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 Boost Converter Passive Devices
        3. 7.2.2.3 EMI Passive Devices
        4. 7.2.2.4 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • RBG|26
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.2.1 Digital Volume Control and Amplifier Output Level

The gain from audio input to speaker terminals is controlled by setting the amplifier’s analog gain level (AAMP) and digital volume control (ADVC). Equation 1 calculates the amplifiers output voltage. Amplifier analog gain setting should be set before powering up the playback channel and shouldn't be changed while the channel is active. The digital volume control can be modified while the channel is active and also allows for soft volume ramp up/down feature to allow for smooth transition of output voltage from one level to another.

Equation 1. TAS2120

where

  • VAMP is the amplifier output voltage in dBV
  • Input is the digital input amplitude in dB with respect to 0 dBFS
  • ADVC is the digital volume control setting, 6 dB to -110 dB in 0.5 dB steps
  • AAMP is the amplifier output level setting, -0.071dBV to 21.0dBV in 0.5017dBV steps.

Amplifier output level settings are presented in dBV (dB relative to 1 Vrms) with a full scale digital audio input (0 dBFS) and the digital volume control set to 0 dB. It should be noted that these levels may not be achievable because of analog clipping in the amplifier, so they should be used to convey gain only.

Table below shows gain settings that can be programmed via the AMP_LVL register. When AMP_LVL is set to less than 9dBV settings, the playback channel is automatically configured to low noise mode or receiver mode of operation.

Table 6-18 Amplifier Output Level Settings
AMP_LVL[5:0]FULL SCALE OUTPUT
dBVVPEAK (V)
0x0021.00015.9
0x0120.49815.0
0x0219.99714.1
0x0319.49513.3
0x0418.99312.6
.........
0x271.4341.7
0x280.9321.6
0x290.4301.5
0x2A-0.0711.4
0x2B-0x3FReservedReserved

When a change in digital volume control occurs, the device ramps the volume to the new setting based on the DVC_SLEW_RATE register bits. If DVC_SLEW_RATE is set to 0x7FFFFF, volume ramp is disabled. This can be used to speed up start up, shutdown and digital volume changes when volume ramp is handled by the system host. When volume ramp is disabled, the input audio data stream should be held at digital silence during shutdown and power up of the device to avoid any clicks and pops.

The device can be put in software based mute by setting DVC_LEVEL to 0x000000 setting.

The digital voltage control registers DVC_LEVEL and DVC_SLEW_RATE registers can be configured using the PPC3 Software Section 6.4.1.

Table 6-19 Digital Volume Control
DVC_LEVEL[23:0]VOLUME (dB)
0x000000Software MUTE
0x00000D (MIN)-110
......
0x4000000 (default)
......
0x7FB261 (MAX)6
Table 6-20 Digital Volume Ramp Rate
DVC_SLEW_RATE[23:0]RAMP RATE @ 48kHz (s)
0x00036A1000ms
...
0x034A514ms (default)
...
0x7FFFFF0 - Ramp disabled