SLASFC6 August   2024 TAS2120

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Boost
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 Boost Converter Passive Devices
        3. 7.2.2.3 EMI Passive Devices
        4. 7.2.2.4 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.3.1.4.3 VDD Y-bridge

TAS2120 uses a Y-bridge output stage for switching the class-D output PWM voltage between the VDD and PVDD supply. When the feature is enabled using EN_Y_BRIDGE_MODE set to high, the device will automatically select the output voltage to switch the output PWM at. When the signal level is low, the output will switch at VDD to enable higher system-level efficiency by reducing the class-D output switching voltage. When the signal level is high, the output switches on the PVDD voltage rail set by the integrated Boost, or external PVDD in the external PVDD mode of operation.

The device monitors the input audio signal level against the programmed Y-bridge mode threshold configured by VDD_MODE_THR_LVL[23:0] register. When the audio signal falls below the threshold, an internal hysteresis timer is enabled. If the signal level remains below the configured YBRIDGE_HYST_TIMER[1:0] for the entire duration of the selected time, the device enters into the lower voltage VDD supply-based PWM switching mode.

When the signal level increases above the VDD_MODE_THR_LVL[23:0] plus VDD_MODE_HYST[23:0], the device starts switching the output PWM signal on PVDD supply without introducing any signal clipping.

The VDD_MODE_THR_LVL[23:0] and VDD_MODE_HYST[23:0] registers can be configured using the PPC3 Software Section 6.4.1.

Table 6-10 VDD Y-bridge hysteresis timer
YBRIDGE_HYST_TIMER[1:0]Configuration
00100us
01 (default)500us
105ms
1150ms
Table 6-11 VDD Y-bridge enable
EN_Y_BRIDGE_MODEConfiguration
0Y-bridge mode is disabled
1 (default)Y-bridge mode is enabled