TAS2120 has integrated SAR ADC to monitor the supply voltage pins VBAT or VBAT_SNS and PVDD. The sensed voltages are used for internal device features, protections and can also be streamed out over digital data bus or read through i2c registers.

The battery voltage can be sensed through either VBAT or VBAT_SNS pins based on the register SEL_VBAT_MODE[1:0]

The monitor ADC samples the VBAT pin at higher rate compared to PVDD pin voltage. This sampling speed can be swapped to prioritize PVDD pin sampling rate over VBAT, for example in case of external PVDD mode of operation.

The VBAT and PVDD monitored voltages are stored in the register VBAT_CNV and PVDD_CNV registers and can be read using i2c commands.

The supply monitors are also used for voltage protection like VBAT under voltage, PVDD over voltage and under voltage and VBAT2S under voltage. The voltage protection features monitors the supply voltages, and shuts down the device when the voltage crosses the protection threshold levels. The device also sets the corresponding fault register and can generate an interrupt on IRQZ pin based on configured interrupt Mask register as described in Section 6.3.2. Once the device is shutdown, the device can be re-powered up using the MODE[1:0] register bits.

PVDD over voltage protection is based on the monitored PVDD voltage compared against a programmable threshold which can be controlled using PVDD_OVLO_TH_SEL in the internal boost mode, and PVDD_OVLO_TH_SEL_EXT_BOOST in the external PVDD mode of operation. The PVDD Over voltage protection is enabled by default and can be disabled by setting PVDD_OV_DET_DIS bit high.