SLASFC5 September   2024 TAS2320

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePathâ„¢ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Supply Voltage Monitors
      5. 6.4.5 Thermal Protection
      6. 6.4.6 Clocks and PLL
        1. 6.4.6.1 Auto clock based wakeup and clock errors
      7. 6.4.7 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 EMI Passive Devices
        3. 7.2.2.3 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. Power Supply Recommendations
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Voltage Limiter and Clipping protection

The supply tracking limiter can be configured using LIM_MODE[1:0] register. In the VBAT voltage mode, the limiter tracks the VBAT supply voltage for voltage limiter and in PVDD voltage mode, the limiter tracks the PVDD voltage for external PVDD mode of use case.

Table 6-19 Limiter mode selection
LIM_MODE[1:0] Configuration
00 (default) Disabled
01 VBAT voltage based limiter
10 PVDD voltage based limiter
11 Reserved
The limiter can be configured to reduce the output signal based on fixed signal threshold level, or it can attenuate signal based on a dynamic threshold which tracks the selected supply voltage. The register bit SUPPLY_HEADROOM_LIM_MODE enables the dynamic supply tracking and can be used to limit the clipping distortion when the supply voltage is varying in the system.
Table 6-20 Limiter dynamic supply headroom tracking mode
SUPPLY_HEADROOM_LIM_MODE Configuration
0(default) Disabled
1 Enabled. Limiter threshold is dynamically changed based as a fixed percentage of monitored supply voltage.

When SUPPLY_HEADROOM_LIM_MODE is set high, the limiter sets the threshold as a fixed percentage of the monitored supply voltage. The limiter begins reducing gain when the output signal level is greater than the threshold configured. For eg, if voltage limiting is desired to be 10% below the supply voltage, then LIM_SLOPE[23:0] is configured as 0.9 and the threshold is calculated as monitored supply voltage multiplied by 1.1. Similarly if the LIM_SLOPE[23:0] is configured at > 1.0, the limiter threshold is set at higher than the supply voltage, and a small amount of controlled clipping occurs.

TAS2320 Limiter with dynamic
                        supply headroom Figure 6-4 Limiter with dynamic supply headroom

When SUPPLY_HEADROOM_LIM_MODE is set low, the limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter can be configured to track selected supply below a programmable inflection point with a minimum threshold value. Figure 6-5below shows the limiter configured to limit to a constant level regardless of the selected supply level. To achieve this behavior, set the limiter maximum threshold to the desired level using LIM_TH_MAX[23:0]. Set the limiter inflection point using LIM_INF_PT[23:0] below the minimum allowable supply setting. The limiter minimum threshold register LIM_TH_MIN[23:0] does not impact limiter behavior in this use case.

TAS2320 Limiter
                    with Fixed Threshold Figure 6-5 Limiter with Fixed Threshold

Figure 6-6 shows how to configure the limiter to track selected supply below a threshold without a minimum threshold. Set the LIM_TH_MAX[23:0] register to the desired threshold and LIM_INF_PT[23:0] register to the desired inflection point where the limiter begins to reduce the threshold with the selected supply. The LIM_SLOPE[23:0] register bits can be used to change the slope of the limiter tracking the supply voltage in V/V. For example, a slope value of 1 V/V reduces the limiter threshold 1 V for every 1 V of drop in the supply voltage. Program the LIM_TH_MIN[23:0] below the minimum of the selected supply to prevent the limiter from having a minimum threshold reduction when tracking the selected supply.

TAS2320 Limiter
                    with Inflection Point Figure 6-6 Limiter with Inflection Point

To achieve a limiter that tracks the selected supply below a threshold, configure the limiter as explained in the previous example, except program the LIM_TH_MIN[23:0] register to the desired minimum threshold. This is shown in Figure 6-7 below.

TAS2320 Limiter
                    with Inflection Point and Minimum Threshold Figure 6-7 Limiter with Inflection Point and Minimum Threshold

The limiter has a configurable attack rate (dB/Sample), hold time ( no of samples) and release rate (db/Sample), which are available via the LIM_ATK_RATE[23:0], LIM_HLD_COUNT[23:0], LIM_RLS_RATE[23:0] register bits.