SLASFC5 September   2024 TAS2320

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Supply Voltage Monitors
      5. 6.4.5 Thermal Protection
      6. 6.4.6 Clocks and PLL
        1. 6.4.6.1 Auto clock based wakeup and clock errors
      7. 6.4.7 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 EMI Passive Devices
        3. 7.2.2.3 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.2.3 Class-D Amplifier

TAS2320 has integrated high performance class-D amplifier with low idle channel noise, low distortion and high PSRR. The Class-D amplifier switches on a clock frequency derived from the SBCLK frequency and is always synchronized to the input clock source. The SAMP_RATE_CFG register enables selection between input clock source based out of multiple of 44.1kHz vs 48kHz multiples.

Table 6-16 Sample rate configuration
SAMP_RATE_CFG Configuration
0 (default) Audio data rate is multiple/sub-multiple of 48ksps
1 Audio data rate is multiple/sub-multiple of 44.1ksps

For improvements in EMI performance the class-D amplifier supports programmable Edge rate control (ERC) and class-D clock spread spectrum modulation (SSM).

The edge rate of class-D can be controlled using CLASSD_OUTPUT_EDGERATE_CTRL[1:0] register. By default the class-D output edge rate is configured to fastest setting to enable high efficiency in the system. The class-D output edge rate can be slowed down using other configuration settings to reduce the EMI energy at high frequency with reduction in efficiency. The exact rate of change of output edge rate varies based on output load conditions, and the values mentioned in the tables below are approximate edge rate levels for default loading conditions.

Table 6-17 Class-D output edge rate control
CLASSD_OUTPUT_EDGERATE_CTRL[1:0] Configuration
00 Class-D output edge rate of 0.5 V/ns
01 Class-D output edge rate of 1.0 V/ns
10 Reserved
11(default) Class-D output edge rate of 2 V/ns

The class-D amplifier has over current protection on each of the output power FETs, including the PVDD High side and the ground power FETs.

The class-D amplifier output impedance can be controlled when the outputs stop switching during Noise gate mode using CLASSD_HIZ_MODE control register.

Table 6-18 Class-D high-Z mode control
CLASSD_HIZ_MODE Configuration
0 (default) Output pulled down with 2.5kΩ
1 Output pulled down with >13kΩ