SLASFC5 September   2024 TAS2320

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Supply Voltage Monitors
      5. 6.4.5 Thermal Protection
      6. 6.4.6 Clocks and PLL
        1. 6.4.6.1 Auto clock based wakeup and clock errors
      7. 6.4.7 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 EMI Passive Devices
        3. 7.2.2.3 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TA = 25 °C, VBAT = 3.6 V, PVDD = 12 V ( External PVDD mode enabled), VDD = 1.8 V, IOVDD = 1.8V, RL = 8Ω + 33µH, fin = 1 kHz, fs = 48 kHz, Gain = 21dBV, SDZ = 1, Noise gate disabled, Measured filter free with an Audio Precision using 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AMPLIFIER PERFORMANCE - EXTERNAL PVDD Mode
POUT_EXT_PVDD Maximum Continuous Output Power - 1% THDN RL = 8 Ω + 33 µH 8.3 W
RL = 4 Ω + 33 µH 14.9 W
POUT_EXT_PVDD Maximum Continuous Output Power - 1% THDN RL = 8 Ω + 33 µH, HW pin control mode 8.3 W
POUT_EXT_PVDD Maximum Continuous Output Power - 10% THDN RL = 8 Ω + 33 µH 10.3 W
RL = 4 Ω + 33 µH 18.4 W
RL = 4 Ω + 33 µH, PVDD=14V 24.5 W
ηSYSTEM_EXT_0.5W System Efficiency at POUT = 0.5W RL = 8 Ω + 33 µH 83.9 %
RL = 4 Ω + 33 µH 80.0 %
ηSYSTEM__EXT_1W System Efficiency at POUT = 1.0W RL = 8 Ω + 33 µH 88.1 %
RL = 4 Ω + 33 µH 84.2 %
ηSYSTEM__EXT_1W System Efficiency at POUT = 1.0W RL = 8 Ω + 33 µH, HW pin control mode 88.1 %
ηSYSTEM_EXT_MAX_POUT System Efficiency at 1% THD+N power Level RL = 8 Ω + 33 µH 93.2 %
RL = 4 Ω + 33 µH 88.5 %
ηSYSTEM_EXT_MAX_POUT System Efficiency at 1% THD+N power Level RL = 8 Ω + 33 µH, HW pin control mode 93.2 %
VN_EXT Idle channel Noise A-Weighted, Gain = 21dBV (Speaker Mode), DAC-Running 14.4 µV
DNR_EXT Dynamic Range A-Weighted, -60 dBFS Method, RL = 8 Ω + 33 µH 114.4 dB
THD+N_EXT Total Harmonic distortion + Noise POUT = 1 W, RL = 8 Ω + 33 µH, fin = 1 kHz 0.003 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 1 kHz 0.004 %
KCP_EXT Click and pop performance All dynamic power up/downs of audio channel except for faults. Includes In/Out of Mute, Power Up and power Down, Noise Gate mode entry and Exit. Measured at Peak A-weighted Voltage. RL = 8 Ω + 33 µH, Input = Digital Silience –68 dBV
VOS_EXT Output Offset Voltage Idle channel –1 1 mV
PSRRPVDD_EXT PVDD power-supply rejection ratio PVDD = 12 V + 200 mVpp, fripple = 217 Hz 115 dB
PVDD = 12 V + 200 mVpp, fripple = 1 kHz 115 dB
PVDD = 12 V + 200 mVpp, fripple = 20 kHz 95 dB
PSRRVBAT_EXT VBAT power-supply rejection ratio VBAT = 3.6 V + 200 mVpp, fripple = 217 Hz 115 dB
VBAT = 3.6 V + 200 mVpp, fripple = 1 kHz 115 dB
VBAT = 3.6 V + 200 mVpp, fripple = 20 kHz 90 dB
PSRRVDD_EXT VDD power-supply rejection ratio VDD = 1.8 V + 200 mVpp, fripple = 217 Hz 110 dB
VDD = 1.8 V + 200 mVpp, fripple = 1 kHz 110 dB
VDD = 1.8 V + 200 mVpp, fripple = 20 kHz 90 dB
TDM Serial Port
PCM Sample Rates and FSYNC Input Frequency 16 192 kHz
SBCLK Input Frequency I2S/TDM Operation 0.512 24.57 MHz
SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation 0.5 ns
RMS Jitter above 40 kHz that can be tolerated without performance degradation 5 ns
SBCLK Cycles per FSYNC in I2S and TDM Modes Values: 64, 96, 128, 192, 256, 384 and 512 64 512 Cycles
PCM Playback Characteristics to fs ≤ 48 kHz
fs Sample Rates 16 48 kHz
Audio Channel Passband LPF Corner Ripple < pass-band ripple 0.454 fs
Audio Channel Passband Ripple 20 Hz to LPF cutoff ± 0.1 dB
Audio Channel Stop Band Attenuation ≥ 0.55 fs 60 dB
≥ 1 fs 65 dB
Audio Channel Group Delay Fin = 1kHz, Class-H mode 31.5 1/fs
Fin = 1kHz, Class-H bypassed 6.5 1/fs
DC to 20kHz, HPF bypassed, Class-H bypassed 11.0 1/fs
DC to 20kHz, HPF bypassed, Class-H mode 37.0 1/fs
PCM Playback Characteristics to fs > 48 kHz
fs Sample Rates 88.2 192 kHz
Audio Channel Passband LPF Corner fs = 96 kHz 0.469 fs
fs = 192 kHz 0.234 fs
Audio Channel Passband Ripple 20 Hz to LPF cutoff ± 0.2 dB
Audio Channel Stop Band Attenuation fs = 96 kHz, fin ≥ 0.55 fs 60 dB
fs = 96 kHz, fin ≥ 1 fs 65 dB
fs = 192 kHz, 0.55 fs ≥ fin ≥ 0.275 fs 60 dB
Audio Channel Group Delay fin=1kHz, fs=96 kHz, Class-H mode 56.7 1/fs
DC to 40kHz, fs=96 kHz, HPF Bypassed, Class-H bypassed 8.6 1/fs
DC to 40kHz, fs=192 kHz, HPF Bypassed, Class-H Mode 117.8 1/fs
Protection Circuits
Thermal shutdown temperature 140 °C
Thermal shutdown retry time 1.5 s
VBAT undervoltage lockout threshold (UVLO) UVLO is asserted 1.9 V
UVLO is released 2.3 V
VDD undervoltage lockout threshold (UVLO) UVLO is asserted 1.4 V
UVLO is released 1.6 V
PVDD undervoltage lockout threshold (UVLO) UVLO is asserted, external PVDD mode only 2.6 V
UVLO is released, external PVDD mode only 2.8 V
PVDD overvoltage lockout threshold (OVLO) OVLO is asserted, OVLO protection enabled.  16 V
Output Short circuit protection Output to Output, Output to GND, Output to PVDD, Output to VBAT,  H-bridge mode 4.1 A
Power up/down Time
TSTDBY Turn ON time from SDZ Asserted to device ready for i2c Command 300 us
TACTIVE Turn ON time from release of Software Shutdown to Amplifier output Active Volume ramping disabled 1.6 ms
Volume ramping enabled 3.9 ms
TTURNOFF Turn OFF time from assertion of Software Shutdown to Amplifier output Hi-Z Volume ramping disabled 0.2 ms
Volume ramping enabled 13.9 ms
Current Consumption - External PVDD Mode
IQ_HW_SD Current consumption in Hardware Shutdown PVDD, SDZ=0 1 uA
VBAT, SDZ=0 0.1 uA
VDD, SDZ=0 0.2 uA
IOVDD, SDZ=0 0.1 uA
IQ_SW_SD Current consumption in Software Shutdown PVDD, All clocks Stopped 1 uA
VBAT, All clocks Stopped 0.1 uA
VDD, All clocks Stopped 12 uA
IOVDD, All clocks Stopped 0.1 uA
IQ_NG Current consumption in Idle channel  PVDD, POUT = 0, Noise gate enabled 0.1 mA
VBAT, POUT = 0, Noise gate enabled 0.15 mA
VDD, POUT = 0, Noise gate enabled 2.2 mA
IOVDD, POUT = 0, Noise gate enabled 0.1 mA
Total Power, POUT = 0, Noise gate enabled 5.3 mW
IQ_IDLE Current consumption in Idle channel PVDD, POUT = 0, Noise gate disabled 0.2 mA
VBAT, POUT = 0, Noise gate disabled 0.5 mA
VDD, POUT = 0, Noise gate disabled 5.6 mA
IOVDD, POUT = 0, Noise gate disabled 0.1 mA
Total Power, POUT = 0, Noise gate disabled 14.0 mW
IQ_IDLE Current consumption in Idle channel, , HW pin control mode PVDD, POUT = 0, Noise gate disabled mA
VBAT, POUT = 0, Noise gate disabled mA
VDD, POUT = 0, Noise gate disabled mA
IOVDD, POUT = 0, Noise gate disabled mA
Total Power, POUT = 0, Noise gate disabled mW
DIGITAL IOs
VIH High-level digital input logic voltage threshold All digital pins  0.7 x IOVDD V
VIL Low-level digital input logic voltage threshold All digital pins 0.3 x IOVDD V
VOH High-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOH = 100µA IOVDD - 0.2 V V
VOL Low-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOL = -100µA 0.2 V
VOL(I2C) Low-level digital output voltage SDA and SCL; IOL = -1mA 0.2 x IOVDD V
VOL(IRQZ) Low-level digital output voltage for open drain output IRQZ pin; IOL = -1mA 0.2 V
IIH Input logic-high leakage for digital inputs All digital pins; Input = IOVDD. -1 1 µA
IIL Input logic-low leakage for digital inputs All digital pins; Input = GND -1 1 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pull down resistance for digital input/IO pins when asserted on All digital pins. Pull down resistance option enabled 18 kΩ