SLASEI9 Data sheet

SLASEI9E july 2017 – july 2023 TAS2505-Q1

PRODUCTION DATA

6.11 SPI Interface Timing

At 25°C, DVDD = 1.8V

PARAMETER		TEST CONDITION	IOVDD=1.8V			IOVDD=3.3V			UNIT
PARAMETER		TEST CONDITION	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
t_sck	SCLK period ⁽¹⁾		100			50			ns
t_sckh	SCLK pulse width High		50			25			ns
t_sckl	SCLK pulse width Low		50			25			ns
t_lead	Enable lead time		30			20			ns
t_lag	Enable lag time		30			20			ns
t_d	Sequential transfer delay		40			20			ns
t_a	Slave DOUT access time				40			40	ns
t_dis	Slave DOUT disable time				40			40	ns
t_su	DIN data setup time		15			15			ns
t_hi	DIN data hold time		15			10			ns
t_v;DOUT	DOUT data valid time				25			18	ns
t_r	SCLK rise time				4			4	ns
t_f	SCLK fall time				4			4	ns

(1) These parameters are based on characterization and are not tested in production.

Figure 6-1 I²S/LJF/RJF Timing in Master Mode

Figure 6-2 I²S/LJF/RJF Timing in Slave Mode

Figure 6-3 DSP Timing in Master Mode

Figure 6-4 DSP Timing in Slave Mode

Figure 6-5 I²C Interface Timing

Figure 6-6 SPI Interface Timing Diagram