SLAS778C February   2013  – September 2021 TAS2505

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  I2S/LJF/RJF Timing in Master Mode
    7. 6.7  I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  DSP Timing in Master Mode
    9. 6.9  DSP Timing in Slave Mode
    10. 6.10 I2C Interface Timing
    11. 6.11 SPI Interface Timing
    12. 6.12 Typical Characteristics
      1. 6.12.1 Class D Speaker Driver Performance
      2. 6.12.2 HP Driver Performance
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Analog I/O
      2. 7.3.2 Audio DAC and Audio Analog Outputs
      3. 7.3.3 DAC
      4. 7.3.4 POR
      5. 7.3.5 CLOCK Generation and PLL
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Pins
      2. 7.4.2 Analog Pins
      3. 7.4.3 Multifunction Pins
      4. 7.4.4 Analog Signals
        1. 7.4.4.1 Analog Inputs AINL and AINR
      5. 7.4.5 DAC Processing Blocks — Overview
      6. 7.4.6 Digital Mixing and Routing
      7. 7.4.7 Analog Audio Routing
      8. 7.4.8 Digital Audio and Control Interface
        1. 7.4.8.1 Digital Audio Interface
        2. 7.4.8.2 Control Interface
          1. 7.4.8.2.1 I2C Control Mode
          2. 7.4.8.2.2 SPI Digital Interface
        3. 7.4.8.3 Device Special Functions
    5. 7.5 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL OSCILLATOR—RC_CLK
Oscillator frequency 8.48 MHz
DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS
See TAS2505 Application Reference Guide (SLAU472) for DAC interpolation filter characteristics.
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 4 Ω (DIFFERENTIAL)
ICN Idle channel noise BTL measurement, class-D gain = 6 dB, Measured as idle-channel noise, A-weighted(2) (1) 37 μVms
Output voltage BTL measurement, class-D gain = 6 dB, –3-dBFS input 1.4 Vrms
THD+N Total harmonic distortion + noise BTL measurement, DAC input = –6 dBFS, class-D gain = 6 dB –73.9 dB
PSRR Power-supply rejection ratio BTL measurement, ripple on SPKVDD = 200 mVPP at 1 kHz 55 dB
Mute attenuation Mute 103 dB
PO Maximum output power SPKVDD = 3.6 V, BTL measurement, CM = 0.9V, class-D gain = 18 dB, THD = 10% 1.1 W
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V, class-D gain = 18 dB, THD = 10% 1.4
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V, class-D gain = 18 dB, THD = 1% 0.8
SPKVDD = 4.2 V, BTL measurement, CM = 0.9V, class-D gain = 18 dB, THD = 1% 1.1
SPKVDD = 5.5 V, BTL measurement, CM = 0.9V, class-D gain = 18 dB 2
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 8 Ω (DIFFERENTIAL)
ICN Idle channel noise BTL measurement, class-D gain = 6 dB, measured as idle-channel noise, A-weighted(2) (1) 35.2 μVms
Output voltage BTL measurement, class-D gain = 6 dB, –3-dBFS input 1.4 Vrms
THD+N Total harmonic distortion + noise BTL measurement, DAC input = –6 dBFS, class-D gain = 6 dB –73.6 dB
PO Maximum output power SPKVDD = 3.6 V, BTL measurement, CM = 0.9 V, class-D gain = 18 dB, THD = 10% 0.7 W
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V, class-D gain = 18 dB, THD = 10% 1
SPKVDD = 5.5 V, BTL measurement, CM = 0.9 V, class-D gain = 18 dB, THD = 10% 1.7
SPKVDD = 3.6 V, BTL measurement, CM = 0.9 V, class-D gain = 18 dB, THD = 1% 0.5
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V, class-D gain = 18 dB, THD = 1% 0.8
SPKVDD = 5.5 V, BTL measurement, CM = 0.9 V, class-D gain = 18 dB, THD = 1% 1.3
ANALOG BYPASS TO CLASS-D SPEAKER AMPLIFIER
Device setup BTL measurement, driver gain = 6 dB, load = 4 Ω (differential), 50 pF, input signal frequency fi = 1 KHz
Voltage gain Input common-mode = 0.9 V 4 V/V
Gain error –1 dBFS (446 mVrms), 1-kHz input signal ±0.7 dB
ICN Idle channel noise Idle channel, IN1L and IN1R ac-shorted to ground, measured as idle-channel noise, A-weighted(2) (1) 32.6 μVms
THD+N Total harmonic distortion + noise –1 dBFS (446 mVrms), 1-kHz input signal –73.7 dB
SHUTDOWN POWER CONSUMPTION
Device setup Power down POR, /RST held low, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 4.2 V, DVDD = 1.8 V
I(AVDD) 1.32 µA
I(DVDD) 0.04 µA
I(IOVDD) 0.68 µA
I(SPKVDD) 2.24 µA
DIGITAL INPUT/OUTPUT
Logic family CMOS
VIH Logic level IIH = 5 μA, IOVDD ≥ 1.6 V 0.7 × IOVDD V
IIH = 5 μA, IOVDD < 1.6 V IOVDD
VIL IIL = 5 μA, IOVDD ≥ 1.6 V –0.3 0.3 × IOVDD V
IIL = 5 μA, IOVDD < 1.6 V 0
VOH IOH = 2 TTL loads 0.8 × IOVDD V
VOL IOL = 2 TTL loads 0.25 V
Capacitive load 10 pF
(1) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(2) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.