SLASFD7 April   2024 TAS2505A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  I2S/LJF/RJF Timing in Master Mode
    7. 5.7  I2S/LJF/RJF Timing in Slave Mode
    8. 5.8  DSP Timing in Master Mode
    9. 5.9  DSP Timing in Slave Mode
    10. 5.10 I2C Interface Timing
    11. 5.11 SPI Interface Timing
    12. 5.12 Typical Characteristics
      1. 5.12.1 Class D Speaker Driver Performance
      2. 5.12.2 HP Driver Performance
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Analog I/O
      2. 7.3.2 Audio DAC and Audio Analog Outputs
      3. 7.3.3 DAC
      4. 7.3.4 POR
      5. 7.3.5 CLOCK Generation and PLL
      6. 7.3.6 Speaker Driver
      7. 7.3.7 Automotive Diagnostics
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Pins
      2. 7.4.2 Analog Pins
      3. 7.4.3 Multifunction Pins
      4. 7.4.4 Analog Signals
        1. 7.4.4.1 Analog Inputs AINL and AINR
      5. 7.4.5 DAC Processing Blocks — Overview
      6. 7.4.6 Digital Mixing and Routing
      7. 7.4.7 Analog Audio Routing
      8. 7.4.8 5V LDO
      9. 7.4.9 Digital Audio and Control Interface
        1. 7.4.9.1 Digital Audio Interface
        2. 7.4.9.2 Control Interface
          1. 7.4.9.2.1 I2C Control Mode
          2. 7.4.9.2.2 SPI Digital Interface
        3. 7.4.9.3 Device Special Functions
    5. 7.5 Register Map
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Circuit Configuration With Internal LDO
        1. 9.2.2.1 Design Requirements
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Pad
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
    8. 10.8 Community Resources
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-9EB939C5-2390-452F-9E1A-D936D4BA4698-low.svgFigure 4-1 RGE Package24-Pin VQFNTop View
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NO.NAME
1SPI_SELISelects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode)
2RSTIReset for logic, state machines, and digital filters; asserted LOW.
3AINLIAnalog single-ended line left input
4AINRIAnalog single-ended line right input
5NCONo Connect (Leave unconnected)
6AVSSGNDAnalog Ground, 0V
7AVDDPWRAnalog Core Supply Voltage, 1.5V to 1.95V, tied internally to the LDO output
8LDO_SELISelect Pin for LDO; ties to either SPKVDD or SPKVSS
9SPKMOClass-D speaker driver inverting output
10SPKVDDPWRClass-D speaker driver power supply
11SPKVSSPWRClass-D speaker driver power supply ground supply
12SPKPOClass-D speaker driver noninverting output
13DINIAudio Serial Data Bus Input Data
14WCLKI/OAudio Serial Data Bus Word Clock
15BCLKI/OAudio Serial Data Bus Bit Clock
16MCLKIMaster CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)
17MISOOSPI Serial Data Output
18GPIO/DOUTI/O/ZGPIO / Audio Serial Bus Output
19SCL/SSZIEither I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state
20SDA/MOSIIEither I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.
21SCLKISerial clock for SPI interface
22IOVDDPWRI/O Power Supply, 1.1V to 3.6V
23DVDDPWRDigital Power Supply, 1.65V to 1.95V
24DVSSGNDDigital Ground, 0V
(1) I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance