SLASFD7 April   2024 TAS2505A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  I2S/LJF/RJF Timing in Master Mode
    7. 5.7  I2S/LJF/RJF Timing in Slave Mode
    8. 5.8  DSP Timing in Master Mode
    9. 5.9  DSP Timing in Slave Mode
    10. 5.10 I2C Interface Timing
    11. 5.11 SPI Interface Timing
    12. 5.12 Typical Characteristics
      1. 5.12.1 Class D Speaker Driver Performance
      2. 5.12.2 HP Driver Performance
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Analog I/O
      2. 7.3.2 Audio DAC and Audio Analog Outputs
      3. 7.3.3 DAC
      4. 7.3.4 POR
      5. 7.3.5 CLOCK Generation and PLL
      6. 7.3.6 Speaker Driver
      7. 7.3.7 Automotive Diagnostics
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Pins
      2. 7.4.2 Analog Pins
      3. 7.4.3 Multifunction Pins
      4. 7.4.4 Analog Signals
        1. 7.4.4.1 Analog Inputs AINL and AINR
      5. 7.4.5 DAC Processing Blocks — Overview
      6. 7.4.6 Digital Mixing and Routing
      7. 7.4.7 Analog Audio Routing
      8. 7.4.8 5V LDO
      9. 7.4.9 Digital Audio and Control Interface
        1. 7.4.9.1 Digital Audio Interface
        2. 7.4.9.2 Control Interface
          1. 7.4.9.2.1 I2C Control Mode
          2. 7.4.9.2.2 SPI Digital Interface
        3. 7.4.9.3 Device Special Functions
    5. 7.5 Register Map
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Circuit Configuration With Internal LDO
        1. 9.2.2.1 Design Requirements
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Pad
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
    8. 10.8 Community Resources
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.12 Register Map

Table 8-5 Summary of Register Map
DecimalHexDESCRIPTION
PAGE NO.REG. NO.PAGE NO.REG. NO.
000x000x00Page Select Register
010x000x01Software Reset Register
02 - 30x000x02 - 0x03Reserved Registers
040x000x04Clock Setting Register 1, Multiplexers
050x000x05Clock Setting Register 2, PLL P and R Values
060x000x06Clock Setting Register 3, PLL J Values
070x000x07Clock Setting Register 4, PLL D Values (MSB)
080x000x08Clock Setting Register 5, PLL D Values (LSB)
09 - 100x000x09 - 0x0AReserved Registers
0110x000x0BClock Setting Register 6, NDAC Values
0120x000x0CClock Setting Register 7, MDAC Values
0130x000x0DDAC OSR Setting Register 1, MSB Value
0140x000x0EDAC OSR Setting Register 2, LSB Value
015 - 240x000x0F - 0x18Reserved Registers
0250x000x19Clock Setting Register 10, Multiplexers
0260x000x1AClock Setting Register 11, CLKOUT M divider value
0270x000x1BAudio Interface Setting Register 1
0280x000x1CAudio Interface Setting Register 2, Data offset setting
0290x000x1DAudio Interface Setting Register 3
0300x000x1EClock Setting Register 12, BCLK N Divider
0310x000x1FAudio Interface Setting Register 4, Secondary Audio Interface
0320x000x20Audio Interface Setting Register 5
0330x000x21Audio Interface Setting Register 6
0340x000x22Reserved Register
035 - 360x000x23 - 0x24Reserved Registers
0370x000x25DAC Flag Register 1
0380x000x26DAC Flag Register 2
039-410x000x27-0x29Reserved Registers
0420x000x2ASticky Flag Register 1
0430x000x2BInterrupt Flag Register 1
0440x000x2CSticky Flag Register 2
0450x000x2DReserved Register
0460x000x2EInterrupt Flag Register 2
0470x000x2FReserved Register
0480x000x30INT1 Interrupt Control Register
0490x000x31INT2 Interrupt Control Register
050-510x000x32-0x33Reserved Registers
0520x000x34GPIO/DOUT Control Register
0530x000x35DOUT Function Control Register
0540x000x36DIN Function Control Register
0550x000x37MISO Function Control Register
0560x000x38SCLK/DMDIN2 Function Control Register
057-590x000x39-0x3BReserved Registers
0600x000x3CDAC Instruction Set
061 - 620x000x3D -0x3EReserved Registers
0630x000x3FDAC Channel Setup Register 1
0640x000x40DAC Channel Setup Register 2
0650x000x41DAC Channel Digital Volume Control Register
066 - 800x000x42 - 0x50Reserved Registers
0810x000x51Dig_Mic Control Register
082 - 1270x000x52 - 0x7FReserved Registers
100x010x00Page Select Register
110x010x01REF, POR and LDO BGAP Control Register
120x010x02LDO Control Register
130x010x03Playback Configuration Register 1
14 - 70x010x04 - 0x07Reserved Registers
180x010x08DAC PGA Control Register
190x010x09Output Drivers, AINL, AINR, Control Register
1100x010x0ACommon Mode Control Register
1110x010x0BHP Over Current Protection Configuration Register
1120x010x0CHP Routing Selection Register
113 - 150x010x0D - 0x0FReserved Registers
1160x010x10Reserved Registers
117 - 190x010x11 - 0x13Reserved Registers
1200x010x14Reserved Registers
1210x010x15Reserved Register
1220x010x16Reserved Registers
1230x010x17Reserved Register
1240x010x18AINL Volume Control Register
1250x010x19AINR Volume Control Register
126 - 440x010x1A - 0x2CReserved Registers
1450x010x2DSpeaker Amplifier Control 1
1460x010x2ESpeaker Volume Control Register
1470x010x2FReserved Register
1480x010x30Speaker Amplifier Volume Control 2
149 - 620x010x31 - 0x3ERight MICPGA Positive Terminal Input Routing Configuration Register
164 - 1210x010x40 - 0x79Reserved Registers
11220x010x7AReference Power Up Delay
1123 - 1270x010x7B - 0x7FReserved Registers
2 - 430 - 1270x02 - 0x2B0x00 - 0x7FReserved Registers
4400x2C0x00Page Select Register
4410x2C0x01DAC Adaptive Filter Configuration Register
442 - 70x2C0x02 - 0x07Reserved
448 - 1270x2C0x08 - 0x7FDAC Coefficients Buffer-A C(0:29)
45 - 5200x2D-0x340x00Page Select Register
45 - 521 - 70x2D-0x340x01 - 0x07Reserved.
45 - 528 - 1270x2D-0x340x08 - 0x7FDAC Coefficients Buffer-A C(30:255)
53 - 610 - 1270x35 - 0x3D0x00 - 0x7FReserved Registers
62 - 7000x3E-0x460x00Page Select Register
62 - 701 - 70x3E-0x460x01 - 0x07Reserved Registers
62 - 708 - 1270x3E-0x460x08 - 0x7FDAC Coefficients Buffer-B C(0:255)
71 - 2550 - 1270x47 - 0x7F0x00 - 0x7FReserved Registers