SLAS978B September   2013  – February 2014 TAS2553

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Terminal Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements/Timing Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  General I2C Operation
      2. 7.3.2  Single-Byte and Multiple-Byte Transfers
      3. 7.3.3  Single-Byte Write
      4. 7.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 7.3.5  Single-Byte Read
      6. 7.3.6  Multiple-Byte Read
      7. 7.3.7  PLL
      8. 7.3.8  Gain Settings
      9. 7.3.9  Class-D Edge Rate Control
      10. 7.3.10 Battery Tracking AGC
    4. 7.4 Device Functional Modes
      1. 7.4.1 Audio Digital I/O Interface
        1. 7.4.1.1 Right-Justified Mode
        2. 7.4.1.2 Left-Justified Mode
        3. 7.4.1.3 I2S Mode
        4. 7.4.1.4 Audio Data Serial Interface Timing (I2S, Left-Justified, Right-Justified Modes)
        5. 7.4.1.5 DSP Mode
        6. 7.4.1.6 DSP Timing
      2. 7.4.2 TDM Mode
      3. 7.4.3 PDM Mode
        1. 7.4.3.1 DOUT Timing - PDM Output Mode
    5. 7.5 Register Map
      1. 7.5.1  Register Map Summary
      2. 7.5.2  Register 0x00: Device Status Register
      3. 7.5.3  Register 0x01: Configuration Register 1
      4. 7.5.4  Register 0x02: Configuration Register 2
      5. 7.5.5  Register 0x03: Configuration Register 3
      6. 7.5.6  Register 0x04: DOUT Tristate Mode
      7. 7.5.7  Register 0x05: Serial Interface Control Register 1
      8. 7.5.8  Register 0x06: Serial Interface Control Register 2
      9. 7.5.9  Register 0x07: Output Data Register
      10. 7.5.10 Register 0x08: PLL Control Register 1
      11. 7.5.11 Register 0x09: PLL Control Register 2
      12. 7.5.12 Register 0x0A: PLL Control Register 3
      13. 7.5.13 Register 0x0B: Battery Tracking Inflection Point Register
      14. 7.5.14 Register 0x0C: Battery Tracking Slope Control Register
      15. 7.5.15 Register 0x0D: Reserved Register
      16. 7.5.16 Register 0x0E: Battery Tracking Limiter Attack Rate and Hysteresis Time
      17. 7.5.17 Register 0x0F: Battery Tracking Limiter Release Rate
      18. 7.5.18 Register 0x10: Battery Tracking Limiter Integration Count Control
      19. 7.5.19 Register 0x11: PDM Configuration Register
      20. 7.5.20 Register 0x12: PGA Gain Register
      21. 7.5.21 Register 0x13: Class-D Edge Rate Control Register
      22. 7.5.22 Register 0x14: Boost Auto-Pass Through Control Register
      23. 7.5.23 Register 0x15: Reserved Register
      24. 7.5.24 Register 0x16: Version Number
      25. 7.5.25 Register 0x17: Reserved Register
      26. 7.5.26 Register 0x18: Reserved Register
      27. 7.5.27 Register 0x19: VBAT Data Register
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application - Digital Audio Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Audio Input/Output
          2. 8.2.1.2.2 Mono/Stereo Configuration
          3. 8.2.1.2.3 Boost Converter Passive Devices
          4. 8.2.1.2.4 EMI Passive Devices
          5. 8.2.1.2.5 Miscellaneous Passive Devices
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Typical Application - Analog Audio Input
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Audio Input/Output
        3. 8.2.2.3 Application Performance Plots
    3. 8.3 Initialization
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
    2. 9.2 Power Supply Sequencing
    3. 9.3 Boost Supply Details
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Package Dimensions
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

9.1 Power Supplies

The TAS2553 requires three power supplies:

  • Boost Input (terminal: VBAT)
    • Voltage: 3.0 V to 5.5 V
    • Max Current: 2.6 A
  • Analog Supply (terminal: AVDD)
    • Voltage: 1.65 V to 1.95 V
    • Max Current: 30 mA
  • Digital I/O Supply (terminal: IOVDD)
    • Voltage: 1.5 V to 3.6 V
    • Max Current: 5 mA

The decoupling capacitors for the power supplies should be placed close to the device terminals. For VBAT, IOVDD and AVDD, a small decoupling capacitor of 0.1 µF should be placed close to the device terminals. Refer to Figure 56 for the schematic.

9.2 Power Supply Sequencing

The power supplies should be started in the following order:

  1. VBAT,
  2. IOVDD,
  3. AVDD.

When the supplies have settled, the EN terminal can be set HIGH to operate the device. The above sequence should be completed before any I2C operation.

9.3 Boost Supply Details

The boost supply (VBAT) and associated passives need to be able to support the current requirements of the device. The peak current limit of the boost is 2.5 A. A minimum of a 10 µF capacitor is recommended on the boost supply to quickly support changes in required current. Refer to Figure 56 for the schematic.

The current requirements can also be reduced by lowering the gain of the amplifier, or in response to decreasing battery through the use of the battery-tracking AGC feature of the TAS2553 described in Battery Tracking AGC.