SLASE69B August 2015 – February 2019 TAS2555
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
| BIT | FIELD | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
|---|---|---|---|---|
| D7-D6 | RESERVED | R/W | 00 | Reserved. Write only reset values. |
| D5 | DSP_CLK | R/W | 0 | DSP clock is generated from
0: output of N_VAL divider in B100_P0_R32 1: directly from PLL Clock |
| D4-D3 | MDAC_CLK | R/W | 00 | MDAC and MADC is clock divider input is
00: NDIV_CLK (N-divider output) 01: MCLK_GPI2. This can be used only if MCLK is multiple of 8*64*Fs or 4*64*Fs(with 48-52% duty-cycle) 10: ICC_GPIO9. This can be used only if MCLK is multiple of 8*64*Fs or 4*64*Fs(with 48-52% duty-cycle) 11: Reserved |
| D2-D1 | BOOST_CLK | R/W | 00 | Boost and Charge-pump divider input is
00: NDIV_CLK (N-divider output) 01: MCLK_GPI2. 10: ICC_GPIO9. 11: Reserved |
| D0 | RESERVED | R/W | 0 | Reserved. Write only reset values. |