SLASEE8B November 2016 – February 2019 TAS2559
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The TAS2559 has two clock error detection blocks. The first is on the Audio Serial Interfaces (ASI). If a clock error is detected on the ASI interfaces, audio artifacts can occur at the Class-D output. When enabled, the ASI clock error detection can mute the device and shutdown the Class-D and DSP core. The clock error detection block is enabled by setting register signal CE1_EN. The ASI1 or ASI2 clocks can be routed to the block for detection using register CE1_IC. Additionally, the clock error can be routed to an interrupt pin, and the sticky bit INT_CLK1 indicates whether the clock error occurred. The second clock error detection block can monitor the DAC, ADC, and PLL clocks. When a clock error is detected, the output is soft-muted and the Class-D powered down. This clock error detection is enabled using bit signal CE2_EN and can be routed to the interrupt pin. It is indicated in the sticky bit INT_CLK2.
When a clocking error occurs, the following sequence should be performed to restart the device.