SLASE86E June   2016  – December 2017 TAS2560

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  I2C Timing Requirements
    7. 7.7  I2S/LJF/RJF Timing in Master Mode
    8. 7.8  I2S/LJF/RJF Timing in Slave Mode
    9. 7.9  DSP Timing in Master Mode
    10. 7.10 DSP Timing in Slave Mode
    11. 7.11 PDM Timing
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  General I2C Operation
      2. 9.3.2  Single-Byte and Multiple-Byte Transfers
      3. 9.3.3  Single-Byte Write
      4. 9.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.3.5  Single-Byte Read
      6. 9.3.6  Multiple-Byte Read
      7. 9.3.7  PLL
      8. 9.3.8  Clock Distribution
      9. 9.3.9  Clock Error Detection
      10. 9.3.10 Class-D Edge Rate Control
      11. 9.3.11 IV Sense
      12. 9.3.12 Boost Control
      13. 9.3.13 Thermal Fold-back
      14. 9.3.14 Battery Guard AGC
      15. 9.3.15 Configurable Boost Current Limit (ILIM)
      16. 9.3.16 Fault Protection
        1. 9.3.16.1 Speaker Over-Current
        2. 9.3.16.2 Analog Under-Voltage
        3. 9.3.16.3 Die Over-Temperature
        4. 9.3.16.4 Clocking Faults
        5. 9.3.16.5 Brownout
      17. 9.3.17 Spread Spectrum vs Synchronized
      18. 9.3.18 IRQs and Flags
      19. 9.3.19 CRC checksum for I2C
      20. 9.3.20 PurePath Console 3 Software TAS2560 Application
    4. 9.4 Device Functional Modes
      1. 9.4.1 Audio Digital I/O Interface
        1. 9.4.1.1 I2S Mode
        2. 9.4.1.2 DSP Mode
        3. 9.4.1.3 DSP Time Slot Mode
        4. 9.4.1.4 Right-Justified Mode (RJF)
        5. 9.4.1.5 Left-Justified Mode (LJF)
        6. 9.4.1.6 Mono PCM Mode
        7. 9.4.1.7 Stereo Application Example - TDM Mode
      2. 9.4.2 PDM MODE
    5. 9.5 Operational Modes
      1. 9.5.1 Hardware Shutdown
      2. 9.5.2 Software Shutdown
      3. 9.5.3 Low Power Sleep
      4. 9.5.4 Software Reset
      5. 9.5.5 Device Processing Modes
        1. 9.5.5.1 Mode 1 - PCM input playback only
        2. 9.5.5.2 Mode 2 - PCM input playback + PCM IVsense output
        3. 9.5.5.3 Mode 2 96k
        4. 9.5.5.4 Mode 3 - PCM input playback + PDM IVsense output
        5. 9.5.5.5 Mode 4 - PDM input playback only
        6. 9.5.5.6 Mode 5 - PDM input playback + PDM IVsense output
    6. 9.6 Programming
      1. 9.6.1 Device Power Up and Un-mute Sequence 8Ω load
      2. 9.6.2 Device Power Up and Un-mute Sequence 4Ω or 6Ω load
      3. 9.6.3 Mute and Device Power Down Sequence
    7. 9.7 Register Map
      1. 9.7.1  Register Map Summary
        1. 9.7.1.1 Register Summary Table
      2. 9.7.2  PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
      3. 9.7.3  RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
      4. 9.7.4  MODE (book=0x00 page=0x00 address=0x02) [reset=1h]
      5. 9.7.5  SPK_CTRL (book=0x00 page=0x00 address=0x04) [reset=5Fh]
      6. 9.7.6  PWR_CTRL_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
      7. 9.7.7  PWR_CTRL_1 (book=0x00 page=0x00 address=0x07) [reset=0h]
      8. 9.7.8  RAMP_CTRL (book=0x00 page=0x00 address=0x08) [reset=1h]
      9. 9.7.9  EDGE_ISNS_BOOST (book=0x00 page=0x00 address=0x09) [reset=83h]
      10. 9.7.10 PLL_CLKIN (book=0x00 page=0x00 address=0x0F) [reset=41h]
      11. 9.7.11 PLL_JVAL (book=0x00 page=0x00 address=0x10) [reset=4h]
      12. 9.7.12 PLL_DVAL_1 (book=0x00 page=0x00 address=0x11) [reset=0h]
      13. 9.7.13 PLL_DVAL_2 (book=0x00 page=0x00 address=0x12) [reset=0h]
      14. 9.7.14 ASI_FORMAT (book=0x00 page=0x00 address=0x14) [reset=2h]
      15. 9.7.15 ASI_CHANNEL (book=0x00 page=0x00 address=0x15) [reset=0h]
      16. 9.7.16 ASI_OFFSET_1 (book=0x00 page=0x00 address=0x16) [reset=0h]
      17. 9.7.17 ASI_OFFSET_2 (book=0x00 page=0x00 address=0x17) [reset=0h]
      18. 9.7.18 ASI_CFG_1 (book=0x00 page=0x00 address=0x18) [reset=0h]
      19. 9.7.19 ASI_DIV_SRC (book=0x00 page=0x00 address=0x19) [reset=0h]
      20. 9.7.20 ASI_BDIV (book=0x00 page=0x00 address=0x1A) [reset=1h]
      21. 9.7.21 ASI_WDIV (book=0x00 page=0x00 address=0x1B) [reset=40h]
      22. 9.7.22 PDM_CFG (book=0x00 page=0x00 address=0x1C) [reset=0h]
      23. 9.7.23 PDM_DIV (book=0x00 page=0x00 address=0x1D) [reset=8h]
      24. 9.7.24 DSD_DIV (book=0x00 page=0x00 address=0x1E) [reset=8h]
      25. 9.7.25 CLK_ERR_1 (book=0x00 page=0x00 address=0x21) [reset=3h]
      26. 9.7.26 CLK_ERR_2 (book=0x00 page=0x00 address=0x22) [reset=3Fh]
      27. 9.7.27 IRQ_PIN_CFG (book=0x00 page=0x00 address=0x23) [reset=21h]
      28. 9.7.28 INT_CFG_1 (book=0x00 page=0x00 address=0x24) [reset=0h]
      29. 9.7.29 INT_CFG_2 (book=0x00 page=0x00 address=0x25) [reset=0h]
      30. 9.7.30 INT_DET_1 (book=0x00 page=0x00 address=0x26) [reset=0h]
      31. 9.7.31 INT_DET_2 (book=0x00 page=0x00 address=0x27) [reset=0h]
      32. 9.7.32 STATUS_POWER (book=0x00 page=0x00 address=0x2A) [reset=0h]
      33. 9.7.33 SAR_VBAT_MSB (book=0x00 page=0x00 address=0x2D) [reset=C0h]
      34. 9.7.34 SAR_VBAT_LSB (book=0x00 page=0x00 address=0x2E) [reset=0h]
      35. 9.7.35 DIE_TEMP_SENSOR (book=0x00 page=0x00 address=0x31) [reset=0h]
      36. 9.7.36 LOW_PWR_MODE (book=0x00 page=0x00 address=0x35) [reset=0h]
      37. 9.7.37 PCM_RATE (book=0x00 page=0x00 address=0x36) [reset=32h]
      38. 9.7.38 CLOCK_ERR_CFG_1 (book=0x00 page=0x00 address=0x4F) [reset=0h]
      39. 9.7.39 CLOCK_ERR_CFG_2 (book=0x00 page=0x00 address=0x50) [reset=11h]
      40. 9.7.40 PROTECTION_CFG_1 (book=0x00 page=0x00 address=0x58) [reset=3h]
      41. 9.7.41 CRC_CHECKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
      42. 9.7.42 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Detailed Design Procedure
          1. 10.2.1.1.1 Mono/Stereo Configuration
          2. 10.2.1.1.2 Boost Converter Passive Devices
          3. 10.2.1.1.3 EMI Passive Devices
          4. 10.2.1.1.4 Miscellaneous Passive Devices
      2. 10.2.2 Application Performance Plots
    3. 10.3 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Power Supply Sequencing
      1. 11.2.1 Boost Supply Details
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Dimensions

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|30
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Device and Documentation Support

13.1 Documentation Support

13.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

13.3 Trademarks

PurePath, E2E are trademarks of Texas Instruments.

13.4 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.