SLASEI7A October 2018 – December 2018 TAS2562
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AD0 | B4 | I | I2C address pin LSB. |
AD1 | B3 | I | I2C address pin LSB+1. |
BGND | D1 | P | Boost ground. Connect to PCB GND plane. |
D2 | |||
D3 | |||
DREG | A6 | P | Digital core voltage regulator output. Bypass to GND with a cap. Do not connect to external load. |
FSYNC | A3 | IO | I2S word clock or TDM frame sync. |
GREG | C4 | P | High-side gate CP regulator output. Do not connect to external load. |
GND | D4 | P | Digital ground. Connect to PCB GDN plane. |
E4 | |||
IRQZ | B5 | O | Open drain, active low interrupt pin. Pull up to VDDD with resistor if optional internal pull up is not used. |
GPIO | C6 | IO | General purpose input/output, no connect if not used. |
OUT_N | E6 | O | Class-D negative output for receiver channel. |
OUT_P | E5 | O | Class-D positive output for receiver channel. |
PGND | D5 | P | Power stage ground. Connect to PCB GND plane. |
D6 | |||
PVDD | F4 | P | Power stage supply. |
F5 | |||
F6 | |||
SBCLK | A2 | IO | I2S/TDM serial bit clock. |
SCL | A4 | I | I2C Clock Pin. Pull up to VDD with a resistor. |
SDA | A5 | IO | I2C Data Pin. Pull up to VDD with a resistor. |
SDIN | B2 | I | I2S/TDM serial data input. |
SDOUT | B1 | IO | I2S/TDM serial data output. |
SDZ | A1 | I | Active low hardware shutdown. |
SW | E1 | P | Boost converter switch input. |
E2 | |||
E3 | |||
VBAT | C1 | P | Battery power supply input. Connect to 2.7 V to 5.5 V supply and decouple with a cap. |
C2 | |||
VBST | F1 | P | Boost converter output. Do not connect to external load. |
F2 | |||
F3 | |||
VDD | B6 | P | Analog, digital, and IO power supply. Connect to 1.8 V supply and decouple to GND with cap. |
VSNS_N | C3 | I | Voltage sense negative input. Connect to Class-D OUT_N output after Ferrite bead filter. |
VSNS_P | C5 | I | Voltage sense positive input. Connect to Class-D OUT_P output after Ferrite bead filter. |