The TAS2764 monitors the PVDD supply voltage and the audio signal to automatically decrease gain when the audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time through end of charge battery conditions. The limiter threshold can be configured to track PVDD below a programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold reduction from PVDD tracking.

The limiter is enabled by setting the LIM_EN bit register to high.

Configurable attack rate, hold time and release rate are provided to shape the dynamic response of the limiter (LIM_ATK_RT[3:0], LIM_HLD_TM[2:0] and LIM_RLS_RT [3:0] register bits).

A maximum level of attenuation applied by the limiter is configurable via the LIM_MAX_ATTN[3:0] register bits. If the limiter mode is attacking and if it reaches the maximum attenuation, gain will not be reduced any further.

The limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter can be configured to track PVDD below a programmable inflection point with a minimum threshold value. Figure 8-6 below shows the limiter configured to limit to a constant level regardless of PVDD level. To achieve this behavior, set the limiter maximum threshold to the desired level via the LIM_TH_MAX[31:0] register bits. Set the limiter inflection point (register bits LIM_INF_PT[31:0]) below the minimum allowable PVDD setting. The limiter minimum threshold, set by register bits LIM_TH_MIN[31:0], does not impact limiter behavior in this use case.

Figure 8-6 Limiter with Fixed Threshold

Figure 8-8 Limiter with Dynamic Threshold

Figure 8-7 Limiter with Inflection Point

Figure 8-9 Limiter with Inflection Point and Minimum Threshold

Figure 8-7 shows how to configure the limiter to track PVDD below a threshold without a minimum threshold. Set the LIM_TH_MAX[31:0] register bits to the desired threshold and LIM_INF_PT[31:0] register bits to the desired inflection point where the limiter will begin reducing the threshold with PVDD. The LIM_SLOPE[31:0] register bits can be used to change the slope of the limiter tracking with PVDD. The default value of 1 V/V will reduce the threshold 1 V for every 1 V of drop in PVDD. More aggressive tracking slopes can be programmed if desired. Program the LIM_TH_MIN[31:0] bits below the minimum PVDD to prevent the limiter from having a minimum threshold reduction when tracking PVDD.

The limiter with a supply tracking slope can be configured in an alternate way. By setting LIM_HR_EN register bit to 1'b1 , a headroom can be specified as a percentage of the supply voltage using a 1V/V slope by setting LIM_DHR[4:0] register bits. For example if a headroom of -10% is specified, the peak output voltage will be set to be 10% higher than PVDD. In this use case presented in Figure 8-8 the limiting begins for signals above the supply voltage and will result in a fixed clipping. If a positive headroom of +10% is specified the peak output voltage will be dynamically set 10% below the current PVDD. In this use case the limiting will begin at signal levels lower than the supply voltage and prevent clipping from occurring.

To achieve a limiter that tracks PVDD only up to a minimum threshold, configure the limiter LIM_TH_MAX [31:0] and LIM_SLOPE[31:0] register bits as in the previous examples. Then additionally set the LIM_TH_MIN[31:0] register bits to the desired minimum threshold. Supply voltage below this minimum threshold will not continue to decrease the signal output voltage. This is shown in Figure 8-9.

By setting register bit LIM_DHYS_EN to low the limiter mechanism depends on settings for maximum/minimum thresholds, inflection point and slope. Once this bit is set high the limiter dynamic headroom is enabled.

When a BOP (Section 8.4.2.8.2) event occurs the limiter updates can be paused (LIM_PDB register bit set to 1'b1) until the BOP fully releases. This can be used to prevent undesired interactions between both protection systems.