SLOSE75B February 2022 – March 2023 TAS2780
PRODUCTION DATA
For VBAT1S supply below 3.4 V the power FETs can go into saturation at higher load currents which could result in device damage due to the FETs connected to PVDD going into thermal runaway.
To prevent the damage the OCP limit needs to be adjusted based on VBAT1S level measured by the internal SAR ADC. The table below presents the thresholds where the OCP will be adjusted and the settings of the registers to program these thresholds.
Once the VBAT1S supply is detected to a level below 3.4 V the device needs to be put in software shutdown or in idle mode before programming the registers.
VBAT1S Range | PVDD OCP Level | Book/Page/Register - New Setting |
---|---|---|
VBAT1S ≥ 3.4 V | 6.6 A | NA |
3.1 V ≤ VBAT1S < 3.4 V | 6 A | B_0/P_0/R_6 - 01 |
2.9 V ≤ VBAT1S < 3.1 V | 5.3 A | B_0/P_0/R_6 - 02 |
2.7 V ≤ VBAT1S < 2.9 V | 4.3 A | B_0/P_FD/R_3A - 7D |
B_0/P_FD/R_3B - See Section 10.7 | ||
B_0/P_FD/R_5C - C0 |
The control of OCP threshold from above is needed only in power modes where VBAT1S is supplied externaly and the Class-D outputs are switching on PVDD (PWR_MODE0, PWR_MODE1).