All supply rails should be bypassed by low-ESR
ceramic capacitors as shown and described in Section 9.2.
To create a low impedance connection to PGND, DGND
and GND and minimize the ground noise, ground planes with multiple conductive epoxy
filled vias should be used in layout.
Specific layout design recommendations should be followed for this device:
- Use wide traces for signals that carry high
current: PVDD, VBAT1S, PGND, DGND, GND and the speaker OUT_P, OUT_N.
- PGND pin should be directly
connected and shorted to the ground plane.
- DGND pin should be directly connected to
the ground plane.
- Connect VSNS_P and VSNS_N as close as possible to the speaker.
- VSNS_P and VSNS_N should be connected between the EMI ferrite filter and the speaker if EMI ferrites are used at the outputs.
- VSNS_P and VSNS_N routing should be separated and shielded from switching signals (interface signals, speaker outputs, bootstrap pins).
- Place bootstrap capacitors as close as possible to the BST pins.
- Place decoupling capacitors of PVDD and
VBAT1S as close as possible to the pins (see Figure 12-1).