The TAS2780 provides a flexible serial audio port. The port can be configured to support a variety of formats including stereo I²S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The SDOUT pin is used to transmit sample streams including speaker voltage and current sense, PVDD voltage, die temperature and channel gain.

The TDM serial audio port supports up to 16 of 32 bit time slots at 44.1/48 kHz or 8 of 32 bit time slots at a 88.2/96 kHz sample rate. Valid SBCLK to FSYNC ratios are 16, 24, 32, 48, 64, 96, 128, 192, 256, and 512. The device can automatically detect the number of time slots and it does not need to be programmed.

By default, the TAS2780 will automatically detect the PCM playback sample rate. This feature can be disabled and the device can manually be configured by setting the AUTO_RATE register bit high.

The SAMP_RATE[2:0] and SAMP_RATIO[3:0] register bits are used to configure the PCM audio sample rate when AUTO_RATE register bit is high (auto detection of TDM sample rate is disabled). The TAS2780 employs a robust clock fault detection engine that will automatically volume ramp down the playback path if FSYNC does not match the configured sample rate (if AUTO_RATE = 1) or the ratio of SBCLK to FSYNC is not supported (minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and ratio, the device will automatically volume ramp the playback path back to the configured volume and resume playback.

When using the auto rate detection the sampling rate and SBCLK to FSYNC ratio detected on the TDM bus are reported back on the read-only register bits FS_RATE[2:0] and FS_RATIO[3:0].

The TAS2780 supports a 12 MHz SBCLK operation. The system will detect or should be manually configured for a ratio of 125 or 250. In this specific ratio the last 32 bit slot should not be used to transmit data over TDM (SDOUT) or ICC (Section 8.4.2.10.1), as data will be truncated.

Figure 8-1 and Figure 8-2 below illustrate the receiver frame parameters required to configure the port for playback. A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge (set by the RX_EDGE register bit). The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format and 1 for an I²S format.

Figure 8-1 TDM RX Time Slot with Left Justification

Figure 8-2 TDM RX Time Slots

The RX_SLEN[1:0] register bits set the length of the RX time slot to 16, 24 or 32 (default) bits. The length of the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits to 16, 20, 24 (default) or 32 bits. The RX port will left justify the audio sample within the time slot by default, but this can be changed to right justification via the RX_JUSTIFY register bit. The TAS2780 supports mono and stereo down mix playback ([L+R]/2). By default the device will playback mono from the time slot equal to the I²C base address offset (set by the ADDR pin) for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot, right time slot or stereo down mix set by the RX_SLOT_L[3:0] and RX_SLOT_R[3:0] register bits.

If time slot selection places reception either partially or fully beyond the frame boundary, the receiver will return a null sample equivalent to a digitally muted sample.

The TDM port can transmit a number of sample streams on the SDOUT pin including speaker voltage sense, speaker current sense, interrupts and status, PVDD voltage, die temperature and channel gain. Figure 8-3 below illustrates the alignment of time slots to the beginning of a frame and how a given sample stream is mapped to time slots.

Figure 8-3 TDM Port TX Diagram

Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin. This can be configured by setting the TX_EDGE register bit. The TX_OFFSET[2:0] register bits define the number of SBCLK cycles between the start of a frame and the beginning of time slot 0. The TDM and ICC TX can either transmit logic 0 or Hi-Z depending on the setting of the TX_FILL register bit. An optional bus keeper will weakly hold the state of SDOUT and ICC pins when all devices driving the bus are Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the TX_KEEPEN register bit. The bus keeper can be configured to hold the bus for only 1LSB or Always using TX_KEEPLN register bit. Additionally, the keeper LSB can be driven for a full cycle or half of cycle using TX_KEEPCY register bit.

TX_FILL register bit is used in mono systems where there is only one amplifier on I²S bus. All the slots unused by the amplifier will be filled with zeros when TX_FILL register bit is set to low.

The SDOUT_HIZ registers from page 0x01 are useful when multiple devices are on the same I²S bus. Each device does not know the configuration of slots in the other devices on the bus. It is required at the system level to program the SDOUT_HIZ registers appropriately, in such way that the settings are done correctly and do not create any contention, internally and externally.

Each sample stream is composed of either one or two 8 bit time slots. Speaker voltage sense and speaker current sense sample streams are 16 bit precision, so they will always utilize two TX time slots. The PVDD and VBAT1S voltage streams are 10 bit precision, and can either be transmitted left justified in a 16 bit word (using two time slots) or can be truncated to 8 bits (the top 8 MSBs) and be transmitted in a single time slot. This is configured by setting PVDD_SLEN and VBAT1S_SLEN register bits. The die temperature and the gain are both 8 bit precision and are transmitted in a single time slot.

The time slot register for each sample stream defines where the MSB transmission begins. By default VSNS_SLOT[5:0] register bits are set to 2 (decimal), the upper 8 MSBs will be transmitted in time slot 2 and the lower 8 LSBs will be transmitted in time slot 3. This sample stream can be individually enabled or disabled by using VSNS_TX register bit. The ISNS_SLOT[5:0] register bits are set by default to 0 (decimal) and the sample stream can be enabled or disabled by using ISNS_TX register bit. The enable/disable feature of the streams is useful to manage limited TDM bandwidth since it may not be necessary to transmit all streams for all devices on the bus.

It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. This will avoid producing unpredictable transmission results in the conflicting bit slots (i.e. the priority is not defined).

The current and voltage values are transmitted at the full 16 bit measured values by default. The IVMON_LEN[1:0] register bits can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits values across multiple slots. The special 12 bit mode is used when only 24 bit I²S/ TDM data can be processed by the host processor. The device should be configured with the voltage-sense slot and current-sense slot off by 1 slot and will consume 3 consecutive 8 bit slots. In this mode the device will transmit the first 12 MSB bits followed by the second 12 MSB bits specified by the preceding slot.

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at the frame boundary.

The time slots for VBAT1S, PVDD and temperature measurements are set using VBAT1S_SLOT[5:0], PVDD_SLOT[5:0] and TEMP_SLOT[5:0] register bits. To enable each of the sample streams, register bits VBAT1S_TX, PVDD_TX and TEMP_TX must be set high. The slot length is selected by VBAT1S_SLEN and PVDD_SLEN register bits.

For TDM final processed audio slot, enable and length settings, use AUDIO_SLOT[5:0], AUDIO_TX and AUDIO_SLEN register bits.

Information about status of slots can be find in STATUS_SLOT[5:0] register bits. STATUS_TX register bit set high enables the status transmit.

The slot configuration for the TX limiter gain reduction can be set between 0 (default) and 63 by setting GAIN_SLOT[5:0] register bits. It is used for ICC (Section 8.4.2.10) and can be either over the TDM bus or ICC bus. To use this feature, the register bit GAIN_TX needs to be set high.