SLOSE75B February 2022 – March 2023 TAS2780
PRODUCTION DATA
Addr | Register | Description | Section |
0x00 | PAGE | Device Page | Section 8.9.6 |
0x01 | SW_RESET | Software Reset | Section 8.9.7 |
0x02 | MODE_CTRL | Device operational mode | Section 8.9.8 |
0x03 | CHNL_0 | Y Bridge and Channel settings | Section 8.9.9 |
0x04 | DC_BLK0 | SAR Filter and DC Path Blocker | Section 8.9.10 |
0x05 | DC_BLK1 | Record DC Blocker | Section 8.9.11 |
0x06 | MISC_CFG1 | Misc Configuration 1 | Section 8.9.12 |
0x07 | MISC_CFG2 | Misc Configuration 2 | Section 8.9.13 |
0x08 | TDM_CFG0 | TDM Configuration 0 | Section 8.9.14 |
0x09 | TDM_CFG1 | TDM Configuration 1 | Section 8.9.15 |
0x0A | TDM_CFG2 | TDM Configuration 2 | Section 8.9.16 |
0x0B | LIM_MAX_ATTN | Limiter | Section 8.9.17 |
0x0C | TDM_CFG3 | TDM Configuration 3 | Section 8.9.18 |
0x0D | TDM_CFG4 | TDM Configuration 4 | Section 8.9.19 |
0x0E | TDM_CFG5 | TDM Configuration 5 | Section 8.9.20 |
0x0F | TDM_CFG6 | TDM Configuration 6 | Section 8.9.21 |
0x10 | TDM_CFG7 | TDM Configuration 7 | Section 8.9.22 |
0x11 | TDM_CFG8 | TDM Configuration 8 | Section 8.9.23 |
0x12 | TDM_CFG9 | TDM Configuration 9 | Section 8.9.24 |
0x13 | TDM_CFG10 | TDM Configuration 10 | Section 8.9.25 |
0x14 | TDM_CFG11 | TDM Configuration 11 | Section 8.9.26 |
0x15 | ICC_CNFG2 | ICC Mode | Section 8.9.27 |
0x16 | TDM_CFG12 | TDM Configuration 12 | Section 8.9.28 |
0x17 | ICLA_CFG0 | Inter Chip Limiter Alignment 0 | Section 8.9.29 |
0x18 | ICLA_CFG1 | Inter Chip Gain Alignment 1 | Section 8.9.30 |
0x19 | DG_0 | Diagnostic Signal | Section 8.9.31 |
0x1A | DVC | Digital Volume Control | Section 8.9.32 |
0x1B | LIM_CFG0 | Limiter Configuration 0 | Section 8.9.33 |
0x1C | LIM_CFG1 | Limiter Configuration 1 | Section 8.9.34 |
0x1D | BOP_CFG0 | Brown Out Prevention 0 | Section 8.9.35 |
0x1E | BOP_CFG1 | Brown Out Prevention 1 | Section 8.9.36 |
0x1F | BOP_CFG2 | Brown Out Prevention 2 | Section 8.9.37 |
0x20 | BOP_CFG3 | Brown Out Prevention 3 | Section 8.9.38 |
0x21 | BOP_CFG4 | Brown Out Prevention 4 | Section 8.9.39 |
0x22 | BOP_CFG5 | BOP Configuration 5 | Section 8.9.40 |
0x23 | BOP_CFG6 | Brown Out Prevention 6 | Section 8.9.41 |
0x24 | BOP_CFG7 | Brown Out Prevention 7 | Section 8.9.42 |
0x25 | BOP_CFG8 | Brown Out Prevention 8 | Section 8.9.43 |
0x26 | BOP_CFG9 | Brown Out Prevention 9 | Section 8.9.44 |
0x27 | BOP_CFG10 | BOP Configuration 10 | Section 8.9.45 |
0x28 | BOP_CFG11 | Brown Out Prevention 11 | Section 8.9.46 |
0x29 | BOP_CFG12 | Brown Out Prevention 12 | Section 8.9.47 |
0x2A | BOP_CFG13 | Brown Out Prevention 13 | Section 8.9.48 |
0x2B | BOP_CFG14 | Brown Out Prevention 14 | Section 8.9.49 |
0x2C | BOP_CFG15 | BOP Configuration 15 | Section 8.9.50 |
0x2D | BOP_CFG17 | Brown Out Prevention 17 | Section 8.9.51 |
0x2E | BOP_CFG18 | Brown Out Prevention 18 | Section 8.9.52 |
0x2F | BOP_CFG19 | Brown Out Prevention 19 | Section 8.9.53 |
0x30 | BOP_CFG20 | Brown Out Prevention 20 | Section 8.9.54 |
0x31 | BOP_CFG21 | BOP Configuration 21 | Section 8.9.55 |
0x32 | BOP_CFG22 | Brown Out Prevention 22 | Section 8.9.56 |
0x33 | BOP_CFG23 | Lowest PVDD Measured | Section 8.9.57 |
0x34 | BOP_CFG24 | Lowest BOP Attack Rate | Section 8.9.57 |
0x35 | NG_CFG0 | Noise Gate 0 | Section 8.9.59 |
0x36 | NG_CFG1 | Noise Gate 1 | Section 8.9.60 |
0x37 | LVS_CFG0 | Low Voltage Signaling | Section 8.9.61 |
0x38 | DIN_PD | Digital Input Pin Pull Down | Section 8.9.62 |
0x3B | INT_MASK0 | Interrupt Mask 0 | Section 8.9.63 |
0x3C | INT_MASK1 | Interrupt Mask 1 | Section 8.9.64 |
0x3D | INT_MASK4 | Interrupt Mask 4 | Section 8.9.65 |
0x40 | INT_MASK2 | Interrupt Mask 2 | Section 8.9.66 |
0x41 | INT_MASK3 | Interrupt Mask 3 | Section 8.9.67 |
0x42 | INT_LIVE0 | Live Interrupt Read-back 0 | Section 8.9.68 |
0x43 | INT_LIVE1 | Live Interrupt Read-back 1 | Section 8.9.69 |
0x44 | INT_LIVE1_0 | Live Interrupt Read-back 1_0 | Section 8.9.70 |
0x47 | INT_LIVE2 | Live Interrupt Read-back 2 | Section 8.9.71 |
0x48 | INT_LIVE3 | Live Interrupt Read-back 3 | Section 8.9.72 |
0x49 | INT_LTCH0 | Latched Interrupt Read-back 0 | Section 8.9.73 |
0x4A | INT_LTCH1 | Latched Interrupt Read-back 1 | Section 8.9.74 |
0x4B | INT_LTCH1_0 | Latched Interrupt Read-back 1_0 | Section 8.9.75 |
0x4F | INT_LTCH2 | Latched Interrupt Read-back 2 | Section 8.9.76 |
0x50 | INT_LTCH3 | Latched Interrupt Read-back 3 | Section 8.9.77 |
0x51 | INT_LTCH4 | Latched Interrupt Read-back 4 | Section 8.9.78 |
0x52 | VBAT_MSB | SAR VBAT1S 0 | Section 8.9.79 |
0x53 | VBAT_LSB | SAR VBAT1S 1 | Section 8.9.80 |
0x54 | PVDD_MSB | SAR PVDD 0 | Section 8.9.81 |
0x55 | PVDD_LSB | SAR PVDD 1 | Section 8.9.82 |
0x56 | TEMP | SAR ADC Conversion 2 | Section 8.9.83 |
0x5C | INT_CLK_CFG | Clock Setting and IRQZ | Section 8.9.84 |
0x5D | MISC_CFG3 | Misc Configuration 3 | Section 8.9.85 |
0x60 | CLOCK_CFG | Clock Configuration | Section 8.9.86 |
0x63 | IDLE_IND | Idle channel current optimization | Section 8.9.87 |
0x64 | SAR_SAMP | SAR Sampling Time | Section 8.9.88 |
0x65 | MISC_CFG4 | Misc Configuration 4 | Section 8.9.89 |
0x67 | TG_CFG0 | Tone Generator | Section 8.9.90 |
0x68 | CLK_CFG | Detect Clock Ration and Sample Rate | Section 8.9.91 |
0x6A | LV_EN_CFG | Class-D and LVS Delays | Section 8.9.92 |
0x6B | NG_CFG2 | Noise Gate 2 | Section 8.9.93 |
0x6C | NG_CFG3 | Noise Gate 3 | Section 8.9.94 |
0x6D | NG_CFG4 | Noise Gate 4 | Section 8.9.95 |
0x6E | NG_CFG5 | Noise Gate 5 | Section 8.9.96 |
0x6F | NG_CFG6 | Noise Gate 6 | Section 8.9.97 |
0x70 | NG_CFG7 | Noise Gate 7 | Section 8.9.98 |
0x71 | PVDD_UVLO | UVLO Threshold | Section 8.9.99 |
0x73 | DMD | DAC Modulator Dither | Section 8.9.100 |
0x7E | I2C_CKSUM | I2C Checksum | Section 8.9.101 |
0x7F | BOOK | Device Book | Section 8.9.102 |