SLOSE75 Data sheet

SLOSE75B February 2022 – March 2023 TAS2780

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RYA|30
- MPQF601

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8.4.2.5 Low Voltage Signaling (LVS)

The TAS2780 monitors the absolute value of the audio stream.

When the input is initially above the programmed fixed threshold set by LVS_FTH[4:0] register bits, the Class-D is supplied by the PVDD rail. When the signal level drops below this threshold for longer than the hysteresis time defined by LVS_HYS[3:0] bits the Class-D supply will switch to VBAT1S (see Figure 8-4).

All values of LVS_HYS[3:0] bit settings will ensure the remaining samples will be output before BYP_EN pin is asserted (high). When multiple devices have BYP_EN pin connected together, any of the devices requiring a supply voltage higher than the threshold will pull the open drain output low.

When the signal level crosses above the programmed fixed threshold set by LVS_FTH[4:0] bits the Class-D supply will switch to PVDD.

The open-drain BYP_EN pin will be de-asserted (actively pulling the output low) after a delay programmed by the LVS_DLY[1:0] register bits . The Y Bridge will switch from the VBAT1S supply to the PVDD supply after a delay programmed by the CDS_DLY[1:0] register bits.

The fixed LVS threshold is set based on the output signal level and is measured in dBFS.

By default, the LVS threshold is configured to be a value relative to the VBAT1S voltage. The LVS_TMODE bit is set to high and the LVS_RTH[3:0] register bits are set to 3'b010 (0.7 V from VBAT1S).

Figure 8-4 Low Voltage Signaling

The LVS fixed thresholds, when CDS_MODE[1:0]=11 (PWR_MODE2 from Section 11.1), can be set using register bits LVS_FTH_LOW[1:0]. When CDS_MODE[1:0]=00 (PWR_MODE1 from Section 11.1) the fixed thresholds should be set with register bits LVS_FTH[4:0].

BOP, Limiter, Thermal Foldback and Thermal Gradient gain attenuations should not be taken into account for calculating LVS threshold.