SLOSE75B February 2022 – March 2023 TAS2780
PRODUCTION DATA
The device enters Hardware Shutdown mode if the SDZ pin is asserted low. In Hardware Shutdown mode, the device consumes the minimum quiescent current from AVDD, IOVDD, PVDDPVDDH and VBAT1S supplies. All registers lose state in this mode and I2C communication is disabled.
By default, when SDZ pin goes low, the device will force a hardware shutdown after a timeout set by the configurable shutdown timer (register bits SDZ_TIMEOUT[1:0]). If SDZ is asserted low while audio is playing, the device will ramp down volume of the audio, stop the Class-D switching, power down analog and digital blocks and finally put the device into Hardware Shutdown mode. The device can also be configured for forced hardware shutdown and in this case it will not attempt to gracefully disable the audio channel. The shutdown mode can be controlled using SDZ_MODE[1:0] register bits.
When SDZ is released, the device will sample the ADDR pin and enter the Software Shutdown mode.