SLOSE75B February 2022 – March 2023 TAS2780
PRODUCTION DATA
A SAR ADC monitors PVDD voltage, VBAT1S voltage and die temperature. The results of these conversions are available via register readback (PVDD_CNV[11:0], VBAT1S_CNV[11:0] and TMP_CNV[7:0] register bits). PVDD and VBAT1S voltage conversions are also used by the limiter and brown out prevention blocks.
By default, VBAT1S conversion is enabled along with PVDD and temperature in both cases, when BOP source is VBAT1S (BOP_SRC=0) or BOP source is PVDD (BOP_SRC=1). To disable VBAT1S conversion set the bit register CONV_VBAT to low.
The ADC runs at a fixed 192 kHz sample rate with a conversion time of 5.2 µs.
Sampling rate for temperature is 10K samples/sec.
PVDD and VBAT1S voltages and the die temperature are calculated using equations from Registers 0x52 to 0x56 of Page 0x00.
The register bits content should always be read from MSB to LSB.