SLOSE86B july   2022  – july 2023 TAS2781

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 SPI Timing Requirements
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Feature Description
      1. 8.3.1 MODE Selection
      2. 8.3.2 Device Address Selection
      3. 8.3.3 SPI Interface
      4. 8.3.4 Register Organization
    4. 8.4  Device Functional Modes
      1. 8.4.1  TDM Serial Audio Port
      2. 8.4.2  Playback Signal Path
        1. 8.4.2.1  Digital Signal Processor
        2. 8.4.2.2  High Pass Filter
        3. 8.4.2.3  Amplifier Inversion
        4. 8.4.2.4  Digital Volume Control and Amplifier Output Level
        5. 8.4.2.5  PVDDL Supply
        6. 8.4.2.6  Y - Bridge
        7. 8.4.2.7  Low Voltage Signaling (LVS)
        8. 8.4.2.8  Noise Gate Mode
        9. 8.4.2.9  Supply Tracking Limiter
        10. 8.4.2.10 Brownout Prevention
        11. 8.4.2.11 ICC Pin and Inter-Chip Communication
        12. 8.4.2.12 Class-D Settings
          1. 8.4.2.12.1 Output Slew Rate Control
          2. 8.4.2.12.2 Synchronization
      3. 8.4.3  SAR ADC
      4. 8.4.4  Current and Voltage (IV) Sense
      5. 8.4.5  Post Filter Feed-Back (PFFB)
      6. 8.4.6  Thermal Foldback
      7. 8.4.7  Over Power Protection
      8. 8.4.8  Low Battery Protection
      9. 8.4.9  Battery Power Limiter
      10. 8.4.10 Clocks
      11. 8.4.11 Ultrasonic
      12. 8.4.12 Echo Reference
      13. 8.4.13 Hybrid-Pro External Boost Controller
    5. 8.5  Operational Modes
      1. 8.5.1 Beep Generator
      2. 8.5.2 Hardware Shutdown
      3. 8.5.3 Mode Control and Software Reset
      4. 8.5.4 Software Shutdown
      5. 8.5.5 Mute Mode
      6. 8.5.6 Active Mode
      7. 8.5.7 Noise Gate Mode
    6. 8.6  Faults and Status in TAS2781
    7. 8.7  Power Sequencing Requirements
    8. 8.8  Digital Input Pull Downs
    9. 8.9  Register Map
      1. 8.9.1   Page = 0x00 Address = 0x00 [Reset = 00h]
      2. 8.9.2   Page = 0x00 Address = 0x01 [Reset = 00h]
      3. 8.9.3   Page = 0x00 Address = 0x02 [Reset = 1Ah]
      4. 8.9.4   Page = 0x00 Address = 0x03 [Reset = 28h]
      5. 8.9.5   Page = 0x00 Address = 0x04 [Reset = 21h]
      6. 8.9.6   Page = 0x00 Address = 0x05 [Reset = 41h]
      7. 8.9.7   Page = 0x00 Address = 0x06 [Reset = 00h]
      8. 8.9.8   Page = 0x00 Address = 0x07 [Reset = 20h]
      9. 8.9.9   Page = 0x00 Address = 0x08 [Reset = 09h]
      10. 8.9.10  Page = 0x00 Address = 0x09 [Reset = 02h]
      11. 8.9.11  Page = 0x00 Address = 0x0A [Reset = 0Ah]
      12. 8.9.12  Page = 0x00 Address = 0x0C [Reset = 10h]
      13. 8.9.13  Page = 0x00 Address = 0x0D [Reset = 13h]
      14. 8.9.14  Page = 0x00 Address = 0x0E [Reset = C2h]
      15. 8.9.15  Page = 0x00 Address = 0x0F [Reset = 40h]
      16. 8.9.16  Page = 0x00 Address = 0x10 [Reset = 04h]
      17. 8.9.17  Page = 0x00 Address = 0x13 [Reset = 08h]
      18. 8.9.18  Page = 0x00 Address = 0x15 [Reset = 00h]
      19. 8.9.19  Page = 0x00 Address = 0x16 [Reset = 12h]
      20. 8.9.20  Page = 0x00 Address = 0x17 [Reset = 80h]
      21. 8.9.21  Page = 0x00 Address = 0x1A [Reset = 00h]
      22. 8.9.22  Page = 0x00 Address = 0x1B [Reset = 62h]
      23. 8.9.23  Page = 0x00 Address = 0x1C [Reset = 36h]
      24. 8.9.24  Page = 0x00 Address = 0x1D [Reset = 00h]
      25. 8.9.25  Page = 0x00 Address = 0x1F [Reset = 01h]
      26. 8.9.26  Page = 0x00 Address = 0x20 [Reset = 2Eh]
      27. 8.9.27  Page = 0x00 Address = 0x34 [Reset = 06h]
      28. 8.9.28  Page = 0x00 Address = 0x35 [Reset = BDh]
      29. 8.9.29  Page = 0x00 Address = 0x36 [Reset = ADh]
      30. 8.9.30  Page = 0x00 Address = 0x37 [Reset = A8h]
      31. 8.9.31  Page = 0x00 Address = 0x38 [Reset = 00h]
      32. 8.9.32  Page = 0x00 Address = 0x3B [Reset = FCh]
      33. 8.9.33  Page = 0x00 Address = 0x3C [Reset = BBh]
      34. 8.9.34  Page = 0x00 Address = 0x3D [Reset = DDh]
      35. 8.9.35  Page = 0x00 Address = 0x40 [Reset = F6h]
      36. 8.9.36  Page = 0x00 Address = 0x41 [Reset = 14h]
      37. 8.9.37  Page = 0x00 Address = 0x42 [Reset = 00h]
      38. 8.9.38  Page = 0x00 Address = 0x43 [Reset = 00h]
      39. 8.9.39  Page = 0x00 Address = 0x44 [Reset = 00h]
      40. 8.9.40  Page = 0x00 Address = 0x47 [Reset = 00h]
      41. 8.9.41  Page = 0x00 Address = 0x48 [Reset = 00h]
      42. 8.9.42  Page = 0x00 Address = 0x49 [Reset = 00h]
      43. 8.9.43  Page = 0x00 Address = 0x4A [Reset = 00h]
      44. 8.9.44  Page = 0x00 Address = 0x4B [Reset = 00h]
      45. 8.9.45  Page = 0x00 Address = 0x4F [Reset = 00h]
      46. 8.9.46  Page = 0x00 Address = 0x50 [Reset = 00h]
      47. 8.9.47  Page = 0x00 Address = 0x51 [Reset = 00h]
      48. 8.9.48  Page = 0x00 Address = 0x52 [Reset = 00h]
      49. 8.9.49  Page = 0x00 Address = 0x53 [Reset = 00h]
      50. 8.9.50  Page = 0x00 Address = 0x54 [Reset = 00h]
      51. 8.9.51  Page = 0x00 Address = 0x55 [Reset = 00h]
      52. 8.9.52  Page = 0x00 Address = 0x56 [Reset = 00h]
      53. 8.9.53  Page = 0x00 Address = 0x5C [Reset = 19h]
      54. 8.9.54  Page = 0x00 Address = 0x5D [Reset = 80h]
      55. 8.9.55  Page = 0x00 Address = 0x60 [Reset = 0Dh]
      56. 8.9.56  Page = 0x00 Address = 0x63 [Reset = 48]
      57. 8.9.57  Page = 0x00 Address = 0x65 [Reset = 08]
      58. 8.9.58  Page = 0x00 Address = 0x67 [Reset = 00h]
      59. 8.9.59  Page = 0x00 Address = 0x68 [Reset = 30h]
      60. 8.9.60  Page = 0x00 Address = 0x6A [Reset = 12h]
      61. 8.9.61  Page = 0x00 Address = 0x6B [Reset = 7Bh]
      62. 8.9.62  Page = 0x00 Address = 0x6C - 0x6E [Reset = 00001Ah]
      63. 8.9.63  Page = 0x00 Address = 0x6F [Reset = 00h]
      64. 8.9.64  Page = 0x00 Address = 0x70 [Reset = 96h]
      65. 8.9.65  Page = 0x00 Address = 0x71 [Reset = 02h]
      66. 8.9.66  Page = 0x00 Address = 0x73 [Reset = 08h]
      67. 8.9.67  Page = 0x00 Address = 0x77 [Reset = 00h]
      68. 8.9.68  Page = 0x00 Address = 0x7A [Reset = 60h]
      69. 8.9.69  Page = 0x00 Address = 0x7E [Reset = 00h]
      70. 8.9.70  Page = 0x00 Address = 0x7F [Reset = 00h]
      71. 8.9.71  Page = 0x01 Address = 0x17 [Reset = D0h]
      72. 8.9.72  Page = 0x01 Address = 0x19 [Reset = 60h]
      73. 8.9.73  Page = 0x01 Address = 0x28 [Reset = 00h]
      74. 8.9.74  Page = 0x01 Address = 0x35 [Reset = 75h]
      75. 8.9.75  Page = 0x01 Address = 0x36 [Reset = 08h]
      76. 8.9.76  Page = 0x01 Address = 0x3D [Reset = 00h]
      77. 8.9.77  Page = 0x01 Address = 0x3E [Reset = 00h]
      78. 8.9.78  Page = 0x01 Address = 0x3F [Reset = 00h]
      79. 8.9.79  Page = 0x01 Address = 0x40 [Reset = 00h]
      80. 8.9.80  Page = 0x01 Address = 0x41 [Reset = 00h]
      81. 8.9.81  Page = 0x01 Address = 0x42 [Reset = 00h]
      82. 8.9.82  Page = 0x01 Address = 0x43 [Reset = 00h]
      83. 8.9.83  Page = 0x01 Address = 0x44 [Reset = 00h]
      84. 8.9.84  Page = 0x01 Address = 0x45 [Reset = 00h]
      85. 8.9.85  Page = 0x01 Address = 0x47 [Reset = AB]
      86. 8.9.86  Page = 0x01 Address = 0x4C [Reset = 00h]
      87. 8.9.87  Page = 0x04 Address = 0x08 - 0x0B [Reset = 034A516Ch]
      88. 8.9.88  Page = 0x04 Address = 0x10 - 0x13 [Reset = 34000000h ]
      89. 8.9.89  Page = 0x04 Address = 0x14 - 0x17 [Reset = 14000000h ]
      90. 8.9.90  Page = 0x04 Address = 0x18 - 0x1B [Reset = 0D333333h]
      91. 8.9.91  Page = 0x04 Address = 0x1C - 0x1F [Reset = 10000000h]
      92. 8.9.92  Page = 0x04 Address = 0x20 - 0x23 [Reset = 0B999999h]
      93. 8.9.93  Page = 0x04 Address = 0x24 - 0x27 [Reset = 0ACCCCCDh]
      94. 8.9.94  Page = 0x04 Address = 0x40 - 0x43 [Reset = 721482C0h]
      95. 8.9.95  Page = 0x04 Address = 0x44 - 0x47 [Reset = 00000258h]
      96. 8.9.96  Page = 0x04 Address = 0x48 - 0x4B [Reset = 40BDB7C0h]
      97. 8.9.97  Page = 0x04 Address = 0x4C - 0x4F [Reset = 3982607Fh]
      98. 8.9.98  Page = 0x04 Address = 0x50 - 0x53 [Reset = 2D6A866Fh]
      99. 8.9.99  Page = 0x04 Address = 0x54 - 0x57 [Reset = 7C5E4E02h]
      100. 8.9.100 Page = 0x05 Address = 0x14 - 0x17 [Reset = 6CCCCCCCh]
      101. 8.9.101 Page = 0x05 Address = 0x1C - 0x1F [Reset = 4CCCCCCh]
      102. 8.9.102 Page = 0x05 Address = 0x20 - 0x23 [Reset = 00000180h]
      103. 8.9.103 Page = 0x05 Address = 0x24 - 0x27 [Reset = 00000000h]
      104. 8.9.104 Page = 0x05 Address = 0x28 - 0x2B [Reset = 79999999h]
      105. 8.9.105 Page = 0x05 Address = 0x2C - 0x2F [Reset = 0538EF34h]
      106. 8.9.106 Page = 0x05 Address = 0x30 - 0x33 [Reset = 40000000h]
      107. 8.9.107 Page = 0x05 Address = 0x34 - 0x37 [Reset = 65AC8C2Fh]
      108. 8.9.108 Page = 0x05 Address = 0x38 - 0x3B [Reset = 50C335D3h]
      109. 8.9.109 Page = 0x05 Address = 0x3C - 0x3F [Reset = 4026E73Ch]
      110. 8.9.110 Page = 0x05 Address = 0x40 - 0x43 [Reset = 32F52CFEh]
      111. 8.9.111 Page = 0x05 Address = 0x44 - 0x47 [Reset = 287A26C4h]
      112. 8.9.112 Page = 0x05 Address = 0x48 - 0x4B [Reset = 2026F30Fh]
      113. 8.9.113 Page = 0x05 Address = 0x4C - 0x4F [Reset = 198A1357h]
      114. 8.9.114 Page = 0x05 Address = 0x50 - 0x53 [Reset = 144960C5h]
      115. 8.9.115 Page = 0x05 Address = 0x54 - 0x57 [Reset = 101D3F2Dh]
      116. 8.9.116 Page = 0x05 Address = 0x58 - 0x5B [Reset = 0CCCCCCCh]
      117. 8.9.117 Page = 0x05 Address = 0x5C - 0x5F [Reset = 0A2AADD1h]
      118. 8.9.118 Page = 0x05 Address = 0x60 - 0x63 [Reset = 08138561h]
      119. 8.9.119 Page = 0x05 Address = 0x64 - 0x67 [Reset = 081385615h]
      120. 8.9.120 Page = 0x05 Address = 0x68 - 0x6B [Reset = 08138561h]
      121. 8.9.121 Page = 0x05 Address = 0x6C - 0x6F [Reset = 08138561h]
      122. 8.9.122 Page = 0x05 Address = 0x70 - 0x73 [Reset = 08138561h]
      123. 8.9.123 Page = 0x05 Address = 0x74 - 0x77 [Reset = 000000BFh]
      124. 8.9.124 Page = 0x05 Address = 0x78 - 0x7B [Reset = 0000000Eh]
      125. 8.9.125 Page = 0x05 Address = 0x7C - 0x7F [Reset = 66676869h]
      126. 8.9.126 Page = 0x06 Address = 0x08 - 0x0B [Reset = 00000000h ]
      127. 8.9.127 Page = 0x06 Address = 0x0C - 0x0F [Reset = 80800000h ]
      128. 8.9.128 Page = 0x06 Address = 0x10 - 0x13 [Reset = C0C00000h ]
      129. 8.9.129 Page = 0x06 Address = 0x14 - 0x17 [Reset = E0E00000h ]
      130. 8.9.130 Page = 0x06 Address = 0x18 - 0x1B [Reset = F0F00000h ]
      131. 8.9.131 Page = 0x06 Address = 0x1C - 0x1F [Reset = F8F80000h ]
      132. 8.9.132 Page = 0x06 Address = 0x20 - 0x23 [Reset = FCFC0000h ]
      133. 8.9.133 Page = 0x06 Address = 0x24 - 0x27 [Reset = FCFC0000h ]
      134. 8.9.134 Page = 0x06 Address = 0x28 - 0x2B [Reset = FCFC0000h ]
      135. 8.9.135 Page = 0x06 Address = 0x2C - 0x2F [Reset = 00000000h ]
      136. 8.9.136 Page = 0x06 Address = 0x30 - 0x33 [Reset = 80000000h ]
      137. 8.9.137 Page = 0x06 Address = 0x34 - 0x37 [Reset = C0000000h ]
      138. 8.9.138 Page = 0x06 Address = 0x38 - 0x3B [Reset = E0000000h ]
      139. 8.9.139 Page = 0x06 Address = 0x3C - 0x3F [Reset = F0000000h ]
      140. 8.9.140 Page = 0x06 Address = 0x40 - 0x43 [Reset = F8000000h ]
      141. 8.9.141 Page = 0x06 Address = 0x44 - 0x47 [Reset = FC000000h ]
      142. 8.9.142 Page = 0x06 Address = 0x48 - 0x4B [Reset = FE000000h ]
      143. 8.9.143 Page = 0x06 Address = 0x4C - 0x4F [Reset = FF000000h ]
      144. 8.9.144 Page = 0x06 Address = 0x50 - 0x53 [Reset = FF800000h ]
      145. 8.9.145 Page = 0x06 Address = 0x54 - 0x57 [Reset = FFC00000h]
      146. 8.9.146 Page = 0x06 Address = 0x58 - 0x5B [Reset = FFE00000h ]
      147. 8.9.147 Page = 0x06 Address = 0x5C - 0x5F [Reset = FFF00000h ]
      148. 8.9.148 Page = 0x06 Address = 0x60 - 0x63 [Reset = FFF00000h ]
      149. 8.9.149 Page = 0x06 Address = 0x64 - 0x67 [Reset = FFF00000h ]
      150. 8.9.150 Page = 0x06 Address = 0x68 - 0x6B [Reset = FFF00000h]
      151. 8.9.151 Page = 0x06 Address = 0x6C - 0x6F [Reset = FFF00000h ]
      152. 8.9.152 Page = 0x08 Address = 0x18 - 0x1B [Reset = 9C000000h ]
      153. 8.9.153 Page = 0x08 Address = 0x28 - 0x2B [Reset = 00000000h ]
      154. 8.9.154 Page = 0x0A Address = 0x48 - 0x4B [Reset = 9C000000h ]
      155. 8.9.155 Page = 0x0A Address = 0x58 - 0x5B [Reset = 00000000h ]
      156. 8.9.156 Page = 0xFD Address = 0x3E [Reset = 4Dh]
    10. 8.10 SDOUT Equations
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
      1. 9.4.1 Mono/Stereo Configuration
      2. 9.4.2 EMI Passive Devices
    5. 9.5 Application Curves
  11. 10Initialization Set Up
    1. 10.1 Initial Device Configuration - Power Up and Software Reset
    2. 10.2 Initial Device Configuration - PWR_MODE0
    3. 10.3 Initial Device Configuration - PWR_MODE1
    4. 10.4 Initial Device Configuration - PWR_MODE2
    5. 10.5 Initial Device Configuration - PWR_MODE3
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Modes
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
  15. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
    2. 14.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.10 Clocks

The device clocking is derived from the SBCLK input clock. The tables below show the valid SBCLK clock frequencies for each sample rate and SBCLK to FSYNC ratio.

If the sample rate is properly configured via the SAMP_RATE[2:0] register bits, no additional configuration is required as long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts. After the clock error is detected, the device will enter a low power halt mode after a time set by CLK_HALT_TIMER[2:0] register bits if DIS_CLK_HALT bit is low. Additionally, the device can automatically power up and down on valid clock signals if CLK_PWRUD register bit is set to high. The device sampling rate should not be changed while this feature is enabled. In this mode the DIS_CLK_HALT bit register should be set low in order for this feature to work properly.

Table 8-5 Supported SBCLK Frequencies [MHz] for 48 kHz Based Sample Rates
Sample Rate (kHz) SBCLK to FSYNC Ratio
16 24 32 48 64 96 125
16 NA NA 0.512 0.768 1.024 1.526 2
24 NA 0.576 0.768 1.152 1.536 2.304 3
32 0.512 0.768 1.024 1.536 2.048 3.072 4
48 0.768 1.152 1.536 2.304 3.072 4.608 6
96 1.536 2.304 3.072 4.608 6.144 9.216 12
192 3.072 4.608 6.144 9.216 12.288 18.432 24
Sample Rate (kHz) SBCLK to FSYNC Ratio
128 192 250 256 384 500 512
16 2.048 3.072 4 4.096 6.144 8 8.192
24 3.072 4.608 6 6.144 9.216 12 12.288
32 4.096 6.144 8 8.192 12.288 16 16384
48 6.144 9.216 12 12.288 18.432 24 24.576
96 12.288 18.432 24 24.576 NA NA NA
192 24.576 NA NA NA NA NA NA
Table 8-6 Supported SBCLK Frequencies [MHz] for 44.1 kHz Based Sample Rates
Sample Rate (kHz) SBCLK to FSYNC Ratio
16 24 32 48 64 96
14.7 NA NA NA 0.7056 0.9408 1.4112
22.05 NA NA 0.7056 1.0584 1.4112 2.1168
29.4 NA 0.7056 0.9408 1.4112 1.8816 2.8224
44.1 0.7056 1.0584 1.4112 2.1168 2.8224 4.2336
88.2 1.4112 2.1168 2.8224 4.2336 5.6448 8.4672
176.4 2.8224 4.2336 5.6448 8.4672 11.2896 16.9344
Sample Rate (kHz) SBCLK to FSYNC Ratio
128 192 256 384 512
14.7 1.8816 2.8224 3.7632 5.6448 7.5264
22.05 2.8224 4.2336 5.6448 8.4672 11.2896
29.4 3.7632 5.6448 8.4672 8.192 15.0528
44.1 5.6448 8.4672 11.2896 16.9344 22.5792
88.2 11.2896 16.9344 22.5792 33.8688 NA
176.4 211.5792 33.8688 NA NA NA