During the power-up sequence, the circuit monitoring the AVDD pin (UVLO) will hold the device in reset (including all configuration registers) until the supply is valid. The device will not exit Hardware Shutdown until AVDD is valid and the SDZ pin is released. Once SDZ is released, the digital core voltage regulator will power up, enabling detection of the operational mode. If AVDD dips below the UVLO threshold, the device will immediately be forced into a reset state.

The device also monitors the PVDDH supply and holds the analog core in power down if the supply is below the UVLO threshold (set by register bits PVDDH_UV_TH[5:0]). If the TAS2781 is in active operation and an UVLO fault occurs, the analog blocks will immediately be powered down to protect the device. These faults are latched and require a transition through HW/SW shutdown to clear the fault. The latched registers will report UVLO faults.

When exiting Software Shutdown to Active (for example: MODE[2:0] bits from 010b to 000b), if PVDDH undervoltage is detected, the device will go back into Software Shutdown and an interrupt (IL_PUVLO) will be flagged. To exit this fault user needs to clear the interrupt and program the device in Software Shutdown using MODE[2:0] bits, before making another attempt to go to Active mode.

A similar situation might occur in PWR_MODE2, if internal PVDDL LDO undervoltage is detected and IL_LDO_UV interrupt is flagged.

The device transitions into Software Shutdown mode if it detects any faults with the TDM clocks such as:

• Invalid SBCLK to FSYNC ratio

• Invalid FSYNC frequency

• Halting of SBCLK or FSYNC clocks

Upon detection of a TDM clock error, the device transitions into Software Shutdown mode as quickly as possible to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back to its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt mask register bit IM_TDMCE is set low. The clock fault is also available for read-back in the live or latched fault status registers (bits IL_TDMCE and IR_TDMCE).

The TAS2781 also monitors die temperature and Class-D load current and will enter software shutdown mode if either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if the appropriate fault interrupt mask register bit is set low for over temperature and for over current. The fault status can also be monitored in the latched fault registers as with the TDM clock error.

Die over temperature and Class-D over current errors can either be latching (i.e. the device will enter Software Shutdown until a HW/SW shutdown sequence is applied) or they can be configured to automatically retry after a prescribed time. This behavior can be configured in the OTE_RETRY and OCE_RETRY register bits (for over temperature and over current). Even in latched mode, the Class-D will not attempt to retry after an over temperature or over current error until the retry time period (Default = 1.5 s) has elapsed. This prevents applying repeated stress to the device in a rapid fashion that could lead to device damage. If the device has been cycled through SW/HW shutdown, the device will only begin to operate after the retry time period. By default the RETRY feature is disabled.

The status registers (and IRQZ pin if enabled, and for un-masked interrupts) also indicate limiter behavior including when the limiter is activated, when PVDDH is below the inflection point, when maximum attenuation has been applied, when the limiter is in infinite hold and when the limiter has muted the audio.

In the situations when the device operates in PWR_MODE2 the PVDDL pin is supplied by an internal LDO. Protection circuits monitor this block and generate faults in case of under voltage, over voltage or if the LDO is over loaded. The device goes into shut down if one of these faults triggers.

The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be pulled up with a resistor to IOVDD. An internal 20 kΩ pull up resistor is provided. It can be accessed by setting the IRQZ_PU register bit of Register 0x04 to high.

The IRQZ interrupt configuration can be set using IRQZ_CFG[1:0] register bits in Register 0x5C. The IRQZ_POL register bit sets the interrupt polarity and IRQZ_CLR register bit allows to clear all the interrupt latch register bits.

Live flag registers are active only when the device is in Active mode of operation. If the device is in Software Shutdown by I²C command or due to any fault condition described below, the live flags will be reset. Latched flags will not be reset in this condition and available for user to read their status.