SLOSE86B july 2022 – july 2023 TAS2781
PRODUCTION DATA
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLK_PWRUD | RW | 0h | Clock based device
power up/power down feature 0h = Disabled 1h = Enabled |
6 | DIS_CLK_HALT | RW | 0h | Clock halt timer
0h = Enable clock halt detection after clock error 1h = Disable clock halt detection after clock error |
5-3 | CLK_HALT_TIMER[2:0] | RW | 3h | Clock halt timer
values 0h = 820 μs 1h = 3.27 ms 2h = 26.21 ms 3h = 52.42 ms (default) 4h = 104.85 ms 5h = 209.71 ms 6h = 419.43 ms 7h = 838.86 ms |
2 | IRQZ_CLR | RW | 0h | Clear interrupt
latch registers 0h = Do not clear 1h = Clear (self clearing bit) |
1-0 | IRQZ_CFG[1:0] | RW | 1h | IRQZ interrupt
configuration. IRQZ will assert 0h = On any unmasked live interrupt 1h = On any unmasked latched interrupt (default) 2h = For 2 - 4 ms one time on any unmasked live interrupt event 3h = For 2 - 4 ms every 4 ms on any unmasked latched interrupt |