SLOSE86B july 2022 – july 2023 TAS2781
PRODUCTION DATA
The TAS2781 Class-D output uses a Y-Bridge configuration to improve efficiency during playback. The LVS () is internally used to select between the PVDDH and PVDDL supplies. This feature is enabled by setting CDS_MODE[1:0] bits to 2'b00 when both PVDDH and PVDDL are supplied to the device. If not configured to Y-bridge mode the device will use only the selected supply for Class-D output even if clipping would otherwise occur. The device can operate using only PVDDH to supply Class-D output. In this configuration the PVDDL can be provided from external supply (register bit PVDDL_MODE=0) or generated by an internal LDO (register bit PVDDL_MODE[7]=1). In this case CDS_MODE[7:6] bits should be set to 2'b10. The TAS2781 Y-Bridge with low power on PVDDL can be used to switch to the PVDDL rail only at very low power when close to idle. This will reduce the Class-D output swing when near idle and limit the current requirements of the PVDDL supply. Set the CDS_MODE[7:6] register to 2'b11 for this mode.
See for details on programming the power mode of operation.
The change to the Class-D supply (PVDDL to PVDDH) determined by the has a delay with respect to input signal crossing threshold and it can be programed using CDS_DLY[1:0] bits of register from .
When in Y-Bridge mode, if the PVDDH falls below (PVDDL + 2.5 V) level, the Y-Bridge will stop switching between supplies and will remain on the PVDDH supply.