SLOSE86B july 2022 – july 2023 TAS2781
PRODUCTION DATA
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | CDS_DLY[1:0] | RW | 0h | Delay (1/fs) of the Y-bridge switching with respect to the input signal. See Table 8-11. |
5-4 | LVS_DLY[1:0] | RW | 1h | Delay (1/fs) of the PWM_CTRL pin signaling with respect to the input signal, when Class H is disabled. See Table 8-12. |
3-0 | LVS_RTH[3:0] | RW | 2h | Relative threshold
for Low Voltage Signaling (headroom from PVDDL voltage). 0h = 0.5 V 1h = 0.6 V 2h = 0.7 V ... Eh = 1.9 V Fh = 2 V |
48 ksps | 96 ksps | |||
---|---|---|---|---|
NG Enabled | NG Disabled | NG Enabled | NG Disabled | |
0h (default) | 8.1 | 6.1 | 12.6 | 9.6 |
1h | 7.1 | 5.1 | 10.6 | 7.6 |
2h | 6.1 | 4.1 | 8.5 | 5.6 |
3h | 5.6 | 3.6 | 7.6 | 4.6 |
48 ksps | 96 ksps | |||
---|---|---|---|---|
NG Enabled | NG Disabled | NG Enabled | NG Disabled | |
0h | 7.8 | 5.8 | 12.1 | 9.1 |
1h (default) | 6.8 | 4.8 | 10.1 | 7.1 |
2h | 5.8 | 3.8 | 8.1 | 5.1 |
3h | 5.1 | 3.1 | 6.6 | 3.6 |