SLOSE86B july   2022  – july 2023 TAS2781

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 SPI Timing Requirements
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Feature Description
      1. 8.3.1 MODE Selection
      2. 8.3.2 Device Address Selection
      3. 8.3.3 SPI Interface
      4. 8.3.4 Register Organization
    4. 8.4  Device Functional Modes
      1. 8.4.1  TDM Serial Audio Port
      2. 8.4.2  Playback Signal Path
        1. 8.4.2.1  Digital Signal Processor
        2. 8.4.2.2  High Pass Filter
        3. 8.4.2.3  Amplifier Inversion
        4. 8.4.2.4  Digital Volume Control and Amplifier Output Level
        5. 8.4.2.5  PVDDL Supply
        6. 8.4.2.6  Y - Bridge
        7. 8.4.2.7  Low Voltage Signaling (LVS)
        8. 8.4.2.8  Noise Gate Mode
        9. 8.4.2.9  Supply Tracking Limiter
        10. 8.4.2.10 Brownout Prevention
        11. 8.4.2.11 ICC Pin and Inter-Chip Communication
        12. 8.4.2.12 Class-D Settings
          1. 8.4.2.12.1 Output Slew Rate Control
          2. 8.4.2.12.2 Synchronization
      3. 8.4.3  SAR ADC
      4. 8.4.4  Current and Voltage (IV) Sense
      5. 8.4.5  Post Filter Feed-Back (PFFB)
      6. 8.4.6  Thermal Foldback
      7. 8.4.7  Over Power Protection
      8. 8.4.8  Low Battery Protection
      9. 8.4.9  Battery Power Limiter
      10. 8.4.10 Clocks
      11. 8.4.11 Ultrasonic
      12. 8.4.12 Echo Reference
      13. 8.4.13 Hybrid-Pro External Boost Controller
    5. 8.5  Operational Modes
      1. 8.5.1 Beep Generator
      2. 8.5.2 Hardware Shutdown
      3. 8.5.3 Mode Control and Software Reset
      4. 8.5.4 Software Shutdown
      5. 8.5.5 Mute Mode
      6. 8.5.6 Active Mode
      7. 8.5.7 Noise Gate Mode
    6. 8.6  Faults and Status in TAS2781
    7. 8.7  Power Sequencing Requirements
    8. 8.8  Digital Input Pull Downs
    9. 8.9  Register Map
      1. 8.9.1   Page = 0x00 Address = 0x00 [Reset = 00h]
      2. 8.9.2   Page = 0x00 Address = 0x01 [Reset = 00h]
      3. 8.9.3   Page = 0x00 Address = 0x02 [Reset = 1Ah]
      4. 8.9.4   Page = 0x00 Address = 0x03 [Reset = 28h]
      5. 8.9.5   Page = 0x00 Address = 0x04 [Reset = 21h]
      6. 8.9.6   Page = 0x00 Address = 0x05 [Reset = 41h]
      7. 8.9.7   Page = 0x00 Address = 0x06 [Reset = 00h]
      8. 8.9.8   Page = 0x00 Address = 0x07 [Reset = 20h]
      9. 8.9.9   Page = 0x00 Address = 0x08 [Reset = 09h]
      10. 8.9.10  Page = 0x00 Address = 0x09 [Reset = 02h]
      11. 8.9.11  Page = 0x00 Address = 0x0A [Reset = 0Ah]
      12. 8.9.12  Page = 0x00 Address = 0x0C [Reset = 10h]
      13. 8.9.13  Page = 0x00 Address = 0x0D [Reset = 13h]
      14. 8.9.14  Page = 0x00 Address = 0x0E [Reset = C2h]
      15. 8.9.15  Page = 0x00 Address = 0x0F [Reset = 40h]
      16. 8.9.16  Page = 0x00 Address = 0x10 [Reset = 04h]
      17. 8.9.17  Page = 0x00 Address = 0x13 [Reset = 08h]
      18. 8.9.18  Page = 0x00 Address = 0x15 [Reset = 00h]
      19. 8.9.19  Page = 0x00 Address = 0x16 [Reset = 12h]
      20. 8.9.20  Page = 0x00 Address = 0x17 [Reset = 80h]
      21. 8.9.21  Page = 0x00 Address = 0x1A [Reset = 00h]
      22. 8.9.22  Page = 0x00 Address = 0x1B [Reset = 62h]
      23. 8.9.23  Page = 0x00 Address = 0x1C [Reset = 36h]
      24. 8.9.24  Page = 0x00 Address = 0x1D [Reset = 00h]
      25. 8.9.25  Page = 0x00 Address = 0x1F [Reset = 01h]
      26. 8.9.26  Page = 0x00 Address = 0x20 [Reset = 2Eh]
      27. 8.9.27  Page = 0x00 Address = 0x34 [Reset = 06h]
      28. 8.9.28  Page = 0x00 Address = 0x35 [Reset = BDh]
      29. 8.9.29  Page = 0x00 Address = 0x36 [Reset = ADh]
      30. 8.9.30  Page = 0x00 Address = 0x37 [Reset = A8h]
      31. 8.9.31  Page = 0x00 Address = 0x38 [Reset = 00h]
      32. 8.9.32  Page = 0x00 Address = 0x3B [Reset = FCh]
      33. 8.9.33  Page = 0x00 Address = 0x3C [Reset = BBh]
      34. 8.9.34  Page = 0x00 Address = 0x3D [Reset = DDh]
      35. 8.9.35  Page = 0x00 Address = 0x40 [Reset = F6h]
      36. 8.9.36  Page = 0x00 Address = 0x41 [Reset = 14h]
      37. 8.9.37  Page = 0x00 Address = 0x42 [Reset = 00h]
      38. 8.9.38  Page = 0x00 Address = 0x43 [Reset = 00h]
      39. 8.9.39  Page = 0x00 Address = 0x44 [Reset = 00h]
      40. 8.9.40  Page = 0x00 Address = 0x47 [Reset = 00h]
      41. 8.9.41  Page = 0x00 Address = 0x48 [Reset = 00h]
      42. 8.9.42  Page = 0x00 Address = 0x49 [Reset = 00h]
      43. 8.9.43  Page = 0x00 Address = 0x4A [Reset = 00h]
      44. 8.9.44  Page = 0x00 Address = 0x4B [Reset = 00h]
      45. 8.9.45  Page = 0x00 Address = 0x4F [Reset = 00h]
      46. 8.9.46  Page = 0x00 Address = 0x50 [Reset = 00h]
      47. 8.9.47  Page = 0x00 Address = 0x51 [Reset = 00h]
      48. 8.9.48  Page = 0x00 Address = 0x52 [Reset = 00h]
      49. 8.9.49  Page = 0x00 Address = 0x53 [Reset = 00h]
      50. 8.9.50  Page = 0x00 Address = 0x54 [Reset = 00h]
      51. 8.9.51  Page = 0x00 Address = 0x55 [Reset = 00h]
      52. 8.9.52  Page = 0x00 Address = 0x56 [Reset = 00h]
      53. 8.9.53  Page = 0x00 Address = 0x5C [Reset = 19h]
      54. 8.9.54  Page = 0x00 Address = 0x5D [Reset = 80h]
      55. 8.9.55  Page = 0x00 Address = 0x60 [Reset = 0Dh]
      56. 8.9.56  Page = 0x00 Address = 0x63 [Reset = 48]
      57. 8.9.57  Page = 0x00 Address = 0x65 [Reset = 08]
      58. 8.9.58  Page = 0x00 Address = 0x67 [Reset = 00h]
      59. 8.9.59  Page = 0x00 Address = 0x68 [Reset = 30h]
      60. 8.9.60  Page = 0x00 Address = 0x6A [Reset = 12h]
      61. 8.9.61  Page = 0x00 Address = 0x6B [Reset = 7Bh]
      62. 8.9.62  Page = 0x00 Address = 0x6C - 0x6E [Reset = 00001Ah]
      63. 8.9.63  Page = 0x00 Address = 0x6F [Reset = 00h]
      64. 8.9.64  Page = 0x00 Address = 0x70 [Reset = 96h]
      65. 8.9.65  Page = 0x00 Address = 0x71 [Reset = 02h]
      66. 8.9.66  Page = 0x00 Address = 0x73 [Reset = 08h]
      67. 8.9.67  Page = 0x00 Address = 0x77 [Reset = 00h]
      68. 8.9.68  Page = 0x00 Address = 0x7A [Reset = 60h]
      69. 8.9.69  Page = 0x00 Address = 0x7E [Reset = 00h]
      70. 8.9.70  Page = 0x00 Address = 0x7F [Reset = 00h]
      71. 8.9.71  Page = 0x01 Address = 0x17 [Reset = D0h]
      72. 8.9.72  Page = 0x01 Address = 0x19 [Reset = 60h]
      73. 8.9.73  Page = 0x01 Address = 0x28 [Reset = 00h]
      74. 8.9.74  Page = 0x01 Address = 0x35 [Reset = 75h]
      75. 8.9.75  Page = 0x01 Address = 0x36 [Reset = 08h]
      76. 8.9.76  Page = 0x01 Address = 0x3D [Reset = 00h]
      77. 8.9.77  Page = 0x01 Address = 0x3E [Reset = 00h]
      78. 8.9.78  Page = 0x01 Address = 0x3F [Reset = 00h]
      79. 8.9.79  Page = 0x01 Address = 0x40 [Reset = 00h]
      80. 8.9.80  Page = 0x01 Address = 0x41 [Reset = 00h]
      81. 8.9.81  Page = 0x01 Address = 0x42 [Reset = 00h]
      82. 8.9.82  Page = 0x01 Address = 0x43 [Reset = 00h]
      83. 8.9.83  Page = 0x01 Address = 0x44 [Reset = 00h]
      84. 8.9.84  Page = 0x01 Address = 0x45 [Reset = 00h]
      85. 8.9.85  Page = 0x01 Address = 0x47 [Reset = AB]
      86. 8.9.86  Page = 0x01 Address = 0x4C [Reset = 00h]
      87. 8.9.87  Page = 0x04 Address = 0x08 - 0x0B [Reset = 034A516Ch]
      88. 8.9.88  Page = 0x04 Address = 0x10 - 0x13 [Reset = 34000000h ]
      89. 8.9.89  Page = 0x04 Address = 0x14 - 0x17 [Reset = 14000000h ]
      90. 8.9.90  Page = 0x04 Address = 0x18 - 0x1B [Reset = 0D333333h]
      91. 8.9.91  Page = 0x04 Address = 0x1C - 0x1F [Reset = 10000000h]
      92. 8.9.92  Page = 0x04 Address = 0x20 - 0x23 [Reset = 0B999999h]
      93. 8.9.93  Page = 0x04 Address = 0x24 - 0x27 [Reset = 0ACCCCCDh]
      94. 8.9.94  Page = 0x04 Address = 0x40 - 0x43 [Reset = 721482C0h]
      95. 8.9.95  Page = 0x04 Address = 0x44 - 0x47 [Reset = 00000258h]
      96. 8.9.96  Page = 0x04 Address = 0x48 - 0x4B [Reset = 40BDB7C0h]
      97. 8.9.97  Page = 0x04 Address = 0x4C - 0x4F [Reset = 3982607Fh]
      98. 8.9.98  Page = 0x04 Address = 0x50 - 0x53 [Reset = 2D6A866Fh]
      99. 8.9.99  Page = 0x04 Address = 0x54 - 0x57 [Reset = 7C5E4E02h]
      100. 8.9.100 Page = 0x05 Address = 0x14 - 0x17 [Reset = 6CCCCCCCh]
      101. 8.9.101 Page = 0x05 Address = 0x1C - 0x1F [Reset = 4CCCCCCh]
      102. 8.9.102 Page = 0x05 Address = 0x20 - 0x23 [Reset = 00000180h]
      103. 8.9.103 Page = 0x05 Address = 0x24 - 0x27 [Reset = 00000000h]
      104. 8.9.104 Page = 0x05 Address = 0x28 - 0x2B [Reset = 79999999h]
      105. 8.9.105 Page = 0x05 Address = 0x2C - 0x2F [Reset = 0538EF34h]
      106. 8.9.106 Page = 0x05 Address = 0x30 - 0x33 [Reset = 40000000h]
      107. 8.9.107 Page = 0x05 Address = 0x34 - 0x37 [Reset = 65AC8C2Fh]
      108. 8.9.108 Page = 0x05 Address = 0x38 - 0x3B [Reset = 50C335D3h]
      109. 8.9.109 Page = 0x05 Address = 0x3C - 0x3F [Reset = 4026E73Ch]
      110. 8.9.110 Page = 0x05 Address = 0x40 - 0x43 [Reset = 32F52CFEh]
      111. 8.9.111 Page = 0x05 Address = 0x44 - 0x47 [Reset = 287A26C4h]
      112. 8.9.112 Page = 0x05 Address = 0x48 - 0x4B [Reset = 2026F30Fh]
      113. 8.9.113 Page = 0x05 Address = 0x4C - 0x4F [Reset = 198A1357h]
      114. 8.9.114 Page = 0x05 Address = 0x50 - 0x53 [Reset = 144960C5h]
      115. 8.9.115 Page = 0x05 Address = 0x54 - 0x57 [Reset = 101D3F2Dh]
      116. 8.9.116 Page = 0x05 Address = 0x58 - 0x5B [Reset = 0CCCCCCCh]
      117. 8.9.117 Page = 0x05 Address = 0x5C - 0x5F [Reset = 0A2AADD1h]
      118. 8.9.118 Page = 0x05 Address = 0x60 - 0x63 [Reset = 08138561h]
      119. 8.9.119 Page = 0x05 Address = 0x64 - 0x67 [Reset = 081385615h]
      120. 8.9.120 Page = 0x05 Address = 0x68 - 0x6B [Reset = 08138561h]
      121. 8.9.121 Page = 0x05 Address = 0x6C - 0x6F [Reset = 08138561h]
      122. 8.9.122 Page = 0x05 Address = 0x70 - 0x73 [Reset = 08138561h]
      123. 8.9.123 Page = 0x05 Address = 0x74 - 0x77 [Reset = 000000BFh]
      124. 8.9.124 Page = 0x05 Address = 0x78 - 0x7B [Reset = 0000000Eh]
      125. 8.9.125 Page = 0x05 Address = 0x7C - 0x7F [Reset = 66676869h]
      126. 8.9.126 Page = 0x06 Address = 0x08 - 0x0B [Reset = 00000000h ]
      127. 8.9.127 Page = 0x06 Address = 0x0C - 0x0F [Reset = 80800000h ]
      128. 8.9.128 Page = 0x06 Address = 0x10 - 0x13 [Reset = C0C00000h ]
      129. 8.9.129 Page = 0x06 Address = 0x14 - 0x17 [Reset = E0E00000h ]
      130. 8.9.130 Page = 0x06 Address = 0x18 - 0x1B [Reset = F0F00000h ]
      131. 8.9.131 Page = 0x06 Address = 0x1C - 0x1F [Reset = F8F80000h ]
      132. 8.9.132 Page = 0x06 Address = 0x20 - 0x23 [Reset = FCFC0000h ]
      133. 8.9.133 Page = 0x06 Address = 0x24 - 0x27 [Reset = FCFC0000h ]
      134. 8.9.134 Page = 0x06 Address = 0x28 - 0x2B [Reset = FCFC0000h ]
      135. 8.9.135 Page = 0x06 Address = 0x2C - 0x2F [Reset = 00000000h ]
      136. 8.9.136 Page = 0x06 Address = 0x30 - 0x33 [Reset = 80000000h ]
      137. 8.9.137 Page = 0x06 Address = 0x34 - 0x37 [Reset = C0000000h ]
      138. 8.9.138 Page = 0x06 Address = 0x38 - 0x3B [Reset = E0000000h ]
      139. 8.9.139 Page = 0x06 Address = 0x3C - 0x3F [Reset = F0000000h ]
      140. 8.9.140 Page = 0x06 Address = 0x40 - 0x43 [Reset = F8000000h ]
      141. 8.9.141 Page = 0x06 Address = 0x44 - 0x47 [Reset = FC000000h ]
      142. 8.9.142 Page = 0x06 Address = 0x48 - 0x4B [Reset = FE000000h ]
      143. 8.9.143 Page = 0x06 Address = 0x4C - 0x4F [Reset = FF000000h ]
      144. 8.9.144 Page = 0x06 Address = 0x50 - 0x53 [Reset = FF800000h ]
      145. 8.9.145 Page = 0x06 Address = 0x54 - 0x57 [Reset = FFC00000h]
      146. 8.9.146 Page = 0x06 Address = 0x58 - 0x5B [Reset = FFE00000h ]
      147. 8.9.147 Page = 0x06 Address = 0x5C - 0x5F [Reset = FFF00000h ]
      148. 8.9.148 Page = 0x06 Address = 0x60 - 0x63 [Reset = FFF00000h ]
      149. 8.9.149 Page = 0x06 Address = 0x64 - 0x67 [Reset = FFF00000h ]
      150. 8.9.150 Page = 0x06 Address = 0x68 - 0x6B [Reset = FFF00000h]
      151. 8.9.151 Page = 0x06 Address = 0x6C - 0x6F [Reset = FFF00000h ]
      152. 8.9.152 Page = 0x08 Address = 0x18 - 0x1B [Reset = 9C000000h ]
      153. 8.9.153 Page = 0x08 Address = 0x28 - 0x2B [Reset = 00000000h ]
      154. 8.9.154 Page = 0x0A Address = 0x48 - 0x4B [Reset = 9C000000h ]
      155. 8.9.155 Page = 0x0A Address = 0x58 - 0x5B [Reset = 00000000h ]
      156. 8.9.156 Page = 0xFD Address = 0x3E [Reset = 4Dh]
    10. 8.10 SDOUT Equations
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
      1. 9.4.1 Mono/Stereo Configuration
      2. 9.4.2 EMI Passive Devices
    5. 9.5 Application Curves
  11. 10Initialization Set Up
    1. 10.1 Initial Device Configuration - Power Up and Software Reset
    2. 10.2 Initial Device Configuration - PWR_MODE0
    3. 10.3 Initial Device Configuration - PWR_MODE1
    4. 10.4 Initial Device Configuration - PWR_MODE2
    5. 10.5 Initial Device Configuration - PWR_MODE3
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Modes
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
  15. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
    2. 14.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TA = 25 °C, PVDDH = 18 V, PVDDL= 3.8 V, AVDD = 1.8 V, IOVDD =1.8 V, RL = 4Ω + 15µH, fin = 1 kHz, fs = 48 kHz, Gain = 21 dBV, SDZ = 1, NG_EN=0, EN_LLSR=0, PWR_MODE1, Measured filter free as in Section 7 (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT and OUTPUT
VIH High-level digital input logic voltage threshold SBLK, FSYNC, SDIN, SCL_nSCS, SDA_SDI 0.7xIOVDD V
VIL Low-level digital input logic voltage threshold SBLK, FSYNC, SDIN, SCL_nSCS, SDA_SDI 0.3 x IOVDD V
VIH(SDZ) High-level digital input logic voltage threshold SDZ 0.7xAVDD V
VIL(SDZ) Low-level digital input logic voltage threshold SDZ 0.3 x AVDD V
VIH(1P8V) High-level digital input logic voltage threshold ICC, NC_SCLK 0.7xNC_V1P8V V
VIL(1P8V) Low-level digital input logic voltage threshold ICC, NC_SCLK 0.3 x NC_V1P8V V
VOH High-level digital output voltage SDOUT; IOH = 100 µA. IOVDD–0.2 V V
VOL Low-level digital output voltage SDOUT; IOH = 100 µA. 0.2 V
VOL(I2C) Low-level digital output voltage SDA_SDI; IOL = -1 mA. 0.2 x IOVDD V
VOH(1P8V) High-level digital output voltage NC_SDO 0.8xNC_V1P8V V
VOL(1P8V) Low-level digital output voltage NC_SDO 0.2xNC_V1P8V V
IIH Input logic-high leakage for digital inputs All digital pins; Input = Supply Rail. –1 1 µA
IIL Input logic-low leakage for digital inputs All digital pins; Input = GND. –1 1 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pull down resistance for IO pins when asserted on 18 kΩ
ROS OUT to VSNS resistors Load disconnected 10 kΩ
IO Output Current Strength

Measured at 0.4 V below supply and 0.4 V above GND.

 8 mA
AMPLIFIER PERFORMANCE
POUT Peak Output Power THD+N = 10 %, PWR_MODE0(1), PWR_MODE1(2) 30 W
Maximum Continuous Output Power THD+N = 1 %, PVDDL = 5 V, PWR_MODE0, PWR_MODE1 25
System Efficiency POUT = 1W, PVDDL = 5 V, PWR_MODE1 84 %
POUT = 1 W, PVDDL = 5 V, PWR_MODE0 79
POUT = 3 W, PVDDL = 5 V, PWR_MODE0 and PWR_MODE1 85
POUT = 8 W, PVDDL = 5 V, PWR_MODE0 and PWR_MODE1 88
THD+N Total Harmonic Distortion and Noise POUT = 1 W,  fin = 1 kHz -84 dB
POUT = 1 W,  fin = 6.667 kHz -84
IMD Inter-Modulation Distortion ITU-R, 19 kHz / 20 kHz, 1:1: 12.5 W -83 dB
VN Idle Channel Noise A-Weighted, 20 Hz - 20 kHz, PWR_MODE0 42 µV
A-Weighted, 20 Hz - 20 kHz, PWR_MODE2 (3) 34
A-Weghted, 20 Hz - 20 kHz, PWR_MODE1 32
Idle Channel Noise with Ultrasonic Chirp (100 us duty cycle, 25 ms period) A-Weghted, 20 Hz - 20 kHz, PWR_MODE3 (4), 1 VPeak, Register 0x73 set to E0h 34
FPWM Class-D PWM Switching Frequency Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=0 384
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1 kHz and 88.2 kHz 352.8
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48 kHz and 96 kHz 384
VOS Output Offset Voltage Idle Mode -1.3 ±0.3 1.3 mV
DNR Dynamic Range A-Weighted, -60 dBFS 110 dB
A-Weighted, -60 dBFS, PWR_MODE2 109
A-Weighted, -60 dBFS, PWR_MODE0 109
SNR Signal to Noise Ratio A-Weighted, Referenced to 1 % THD+N Output Level 110 dB
A-Weighted, Referenced to 1 % THD+N Output Level, PWR_MODE2(1) 110
A-Weighted, Referenced to 1 % THD+N Output Level, PWR_MODE0 109
KCP Click and Pop Performance Idle mode, into and out of Shutdown mode, A-weighted 0.8 mV
Full Scale Output Voltage fs ≤ 48 kHz 21 dBV
Minimum Programmable Gain fs ≤ 48 kHz 11 dBV
Maximum Programmable Gain fs ≤ 48 kHz 21
Programmable Output Level Step Size 0.5 dB
Mute attenuation Device in Software Shutdown or Muted in normal operation 108 dB
Chip to Chip Group Delay -1 1 µs
PVDDH Power Supply Rejection Ratio PVDDH = 18 V + 200 mVpp, fripple = 217 Hz 118 dB
PVDDH = 18 V + 200 mVpp, fripple = 1 kHz 110
PVDDH = 18 V + 200 mVpp, fripple = 20 kHz 98
PVDDL Power Supply Rejection Ratio PVDDL = 5 V + 200 mVpp, fripple = 217 Hz 114 dB
PVDDL = 5 V + 200 mVpp, fripple = 1 kHz 109
PVDDL = 5 V + 200 mVpp, fripple = 20 kHz 93
AVDD Power Supply Rejection Ratio AVDD = 1.8 V + 200 mVpp, fripple = 217 Hz 105 dB
AVDD = 1.8 V + 200 mVpp, fripple = 1 kHz 103
AVDD = 1.8 V + 200 mVpp, fripple = 20 kHz 88
Power Supply Inter-modulation PVDDH, 217 Hz, 100-mVpp, Input f = 1 kHz @ 400 mW -120 dB
PVDDL,217 Hz, 100-mVpp, Input f = 1 kHz @ 400 mW -120
AVDD, 217 Hz, 100-mVpp, Input f = 1 kHz @ 400 mW -80
IOVDD 217 Hz, 100-mVpp, Input f = 1 kHz @ 400 mW -117
Turn ON Time from Release of Software Shutdown No Volume Ramping 1.13 ms
Volume Ramping 6.73
Turn OFF Time From Assertion of Software Shutdown to Amp Hi-Z No Volume Ramping 0.56 ms
Volume Ramping 6
Out of Hardware Shutdown to first I2C command 1 ms
SDZ timeout Exiting HW Shutdown 2 6 23.8 ms
Turn OFF Time when Software Shutdow fs = 48 ksps, DVC_RMP_RT[3:2] = 3h (disabled). Multiply by 48/fs for differet sampling rate. 1 ms
fs = 48 ksps, DVC_RMP_RT[3:2] = 0h (enabled). Multiply by 48/fs for different sampling rate. 12.5
DIE TEMPERATURE
SENSOR
Resolution 8 bits
Minimum Temperature Measurement Range -40 °C
Maximum Temperature Measurement Range 150 °C
Die Temperature Resolution 1 °C
Die Temperature Accuracy -5 5 °C
VOLTAGE
MONITOR
Resolution 12 bits
PVDDH Measurement Range Minimum Level 2 V
Maximum Level 23
PVDDH Resolution 22.5 mV
PVDDH Accuracy 2 V ≤ PVDDHV ≤ 23 V ±60 mV
PVDDL Measurement Range Minimum Level 2.3 V
Maximum Level 6
PVDDL Resolution 20 mV
PVDDL Accuracy 2.3 V≤ PVDDL ≤ 6 V ±20 mV
TDM SERIAL AUDIO PORT
Minimum PCM Sample Rates and FSYNC Input Frequency 14.7 kHz
Maximum PCM Sample Rates and FSYNC Input Frequency 192
Minimum SBCLK Input Frequency I2S/TDM Operation 0.512 MHz
Maximum SBCLK Input Frequency I2S/TDM Operation 24.576
SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation 0.5 ns
RMS Jitter above 40 kHz that can be tolerated without performance degradation 1
Minimum SBCLK Cycles per FSYNC in I2S and TDM Modes Other Values: 24, 32, 48, 64, 96, 125, 128, 192, 250, 256, 384, 500 16 Cycles
Maximum SBCLK Cycles per FSYNC in I2S and TDM Modes Other Values: 24, 32, 48, 64, 96, 125, 128, 192, 250, 256, 384, 500 512
PCM PLAYBACK
CHARACTERISTICS fs ≤ 48 kHz
fs Minimum Sample Rate 14.7 kHz
Maximum Sample Rate 48
Passband Frequency Meeting Ripple 0.454 fs
Passband Ripple 20 Hz to LPF cutoff frequency -0.5 0.5 dB
Stop Band Attenuation ≥ 0.55 fs 60 dB
≥ 1 fs 65
Group Delay (Including Noise Gate) DC to 0.454 fs, DC blocker disabled, Class-H disabled 31 1/fs
DC to 0.454 fs, DC blocker disabled, Class-H enabled 221
PCM PLAYBACK
CHARACTERISTICS fs > 48 kHz
fs Minimum Sample Rates 88.2 kHz
Maximum Sample Rate 192
Frequency for Passband Ripple fs = 96 kHz 0.437 fs
Passband 3db Frequency fs = 96 kHz 0.459 fs
Passband Ripple DC to LPF cutoff frequency -0.5 0.5 dB
Stop Band Attenuation ≥ 0.56 fs 60 dB
≥ 1 fs 65
Group Delay (Including Noise Gate) DC to 0.375 fs, DC blocker disabled, Class-H disabled 51 1/fs
DC to 0.375 fs, DC blocker disabled, Class-H enabled 242
SPEAKER CURRENT SENSE
Resolution 16 bits
DNR Dynamic Range Un-weighted, relative to 0 dBFS 70 dB
THD+N Total Harmonic Distortion and Noise Pout = 15 W -61 dB
Full Scale Input Current Measured at -6 dBFS. Re-scaled at 0 dBFS. 5 A
Differential Mode Gain Pout = 1W, using a 40Hz - 40dBFS pilot tone 0.98 1.02
Frequency Response 20 Hz - 20 kHz -0.1 0.1 dB
Group Delay 22 1/fs
SPEAKER VOLTAGE SENSE
Resolution 16 bits
DNR Dynamic Range Un-weighted, relative 0 dBFS 73 dB
THD+N Total Harmonic Distortion and Noise Pout = 15 W -68 dB
Full Scale Input Voltage 16 VPK
Differential Mode Gain Pout = 1W, using a 40Hz - 40dBFS pilot tone 0.98 1.02
Frequency Response 20 Hz - 20 kHz -0.1 0.1 dB
Group Delay 22 1/fs
SPEAKER VOLTAGE/CURRENT SENSE RATIO
Gain Linearity Pout ≥ 40 mW to 0.1% THD+N, using a 40 Hz -40 dBFS pilot tone, PWR_MODE0 -1 1 %
Gain Linearity Pout ≥ 80 mW to 0.1% THD+N, using a 40 Hz -40 dBFS pilot tone, PWR_MODE1 -1 1 %
Gain error over temperature -20 °C to 70 °C, Pout = 1 W ±0.6 %
Phase Error between V and I 300 ns
PROTECTION CIRCUITRY
Brownout Prevention Latency to First Attack BOP_SRC=1 400 µs
Thermal Shutdown Temperature 145 °C
Thermal Shutdown Retry OTE_RETRY=1 1.5 s
Output Over Current Limit on PVDDH Output to Output, Output to GND or Output to PVDDH Short 5.5 6.7 A
Output Over Current Limit on PVDDL Output to Output, Output to GND or Output to PVDDL Short 2 2.6 A
PVDDL Undervoltage Lockout Threshold UVLO is asserted 2 V
UVLO is de-asserted 2.16
AVDD Undervoltage Lockout Threshold UVLO is asserted 1.45 V
UVLO is de-asserted 1.51
IOVDD Undervoltage Lockout Threshold UVLO is asserted 1.13 V
UVLO is de-asserted 1.25
PVDDL Internal LDO Undervoltage Lockout Threshold UVLO is asserted 4.1 V
CLASS-H CONTROLLER
Look Ahead Time Sampling Rates 48 kHz and 96 kHz 4.8 ms
BEEP PIN GENERATOR
fIN SDZ Pin Input PWM signal frequency 25.6 192 kHz
fIN NC_SCLK Pin Input PWM signal frequency 1.6 12 kHz
TYPICAL CURRENT CONSUMPTION
Hardware Shutdown SDZ = 0, PVDDH 0.05 µA
SDZ = 0, PVDDL 0.01
SDZ = 0, AVDD 0.14
SDZ = 0, IOVDD 0.005
Software Shutdown All Clocks Stopped, PVDDH 0.05 µA
All Clocks Stopped, PVDDL 0.5
All Clocks Stopped, AVDD 10
All Clocks Stopped, IOVDD 0.52
Noise Gate Mode fs = 48 kHz, PVDDH 0.012 mA
fs = 48 kHz, PVDDL 0.13
fs = 48 kHz, AVDD 8.2
fs = 48 kHz, IOVDD 0.01
Idle Mode - PWR_MODE1 fs = 48 kHz, PVDDH 0.04 mA
fs = 48 kHz, PVDDL 2.2
fs = 48 kHz, AVDD, IV Sense = Enabled 15.5
fs = 48 kHz, AVDD, IV Sense = Disabled 11.8
fs = 48 kHz, IOVDD 0.02
Idle Mode - PWR_MODE2 fs = 48 kHz, PVDDH 3 mA
fs = 48 kHz, AVDD, IV Sense = Enabled 15.5
fs = 48 kHz, AVDD, IV Sense = Disabled 11.8
fs = 48 kHz, IOVDD 0.02
Idle Mode - PWR_MODE0 fs = 48 kHz, PVDDH 2.3 mA
fs = 48 kHz, PVDDL 2.1
fs = 48 kHz, AVDD, IV Sense = Enabled 15.5
fs = 48 kHz, AVDD, IV Sense = Disabled 11.8
fs = 48 kHz, IOVDD 0.02
(1) PWR_MODE0: CDS_MODE=10, PVDDL_MODE=0
(2) PWR_MODE1: CDS_MODE=00, PVDDL_MODE=0
(3) PWR_MODE2: CDS_MODE=11, PVDDL_MODE=1
(4) PWR_MODE3: CDS_MODE=01, PVDDL_MODE=0