The TAS2781 provides a flexible TDM serial audio port. The port can be configured to support a variety of formats including stereo I²S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The SDOUT pin is used to transmit sample streams including PVDDL voltage, PVDDH voltage, die temperature, status, audio for echo cancelation.

By default, the TAS2781 will automatically detect the PCM playback sample rate (AUTO_RATE= 0). This can be disabled and manually configured by setting the AUTO_RATE bit of register in to high.

The TDM serial audio port valid SBCLK to FSYNC ratios are presented in register in . The device will automatically detect the number of time slots and it does not need to be programmed.

The SAMP_RATE[2:0] and SBLK_FS_RATIO[5:0] register bits are used to configure the PCM audio sample rate when AUTO_RATE register bit is high (auto detection of TDM sample rate is disabled). The TAS2781 employs a robust clock fault detection engine that will automatically volume ramp down the playback path if FSYNC does not match the configured sample rate (if AUTO_RATE = 1) or the ratio of SBCLK to FSYNC is not supported (minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and ratio, the device will automatically volume ramp the playback path back to the configured volume and resume playback.

When using the auto rate detection the sampling rate and SBCLK to FSYNC ratio detected on the TDM bus is reported back on the read-only bits FS_RATIO[5:0] and FS_RATE[2:0] of registers in ] and in .

A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge (set by the RX_EDGE register bit). The RX_OFF[4:0] register bits define the number of SBCLK cycles from the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format and 1 for an I²S format.

The RX_SLEN[1:0] register bits set the length of the RX time slot to 16, 24 or 32 (default) bits. The length of the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will left justify the audio sample within the time slot by default, but this can be changed to right justification via the RX_JSTF register bit. The TAS2781 supports mono and stereo down mix playback ([L+R]/2). By default the device will playback mono from the time slot equal to the I²C base address offset (set by the ADDR pin) for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot, right time slot or stereo down mix set by the RX_SLOT_R[3:0] and RX_SLOT_L[3:0] register bits.

If time slot selection places reception either partially or fully beyond the frame boundary, the receiver will return a null sample equivalent to a digitally muted sample.

The TDM port can transmit a number of sample streams on the SDOUT pin: speaker voltage sense, speaker current sense, interrupts and status, PVDDH voltage and die temperature.

Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin. This can be configured by setting the TX_EDGE register bit. The TX_OFF[2:0] register bits define the number SBCLK cycles between the start of a frame and the beginning of time slot 0. This would typically be programmed to 0 for Left Justified format and 1 for I²S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the setting of the TX_FILL register bit. An optional bus keeper will weakly hold the state of SDOUT pin when all devices are driving Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the TX_KEEPEN register bit. The bus keeper can be configured to hold the bus for only 1 LSB or Always (permanent) using TX_KEEPLN register bit. Additionally, the keeper LSB can be driven for a full cycle or half of cycle using TX_KEEPCY register bit.

TX_FILL is used in mono system where there is only one amplifier on I²S bus. All the slots unused by the amplifier will be filled with zeros when TX_FILL is set to low. The TX bits mentioned are in the register in .

The SDOUT_HIZ registers from page 0x01 are useful when multiple devices are on the same I²S bus. Each device does not know configuration of slots in the other devices on the bus. It is required at the system level to program the SDOUT_HIZ registers appropriately, in such way that the settings are done correctly and do not create any contention both internally and externally.

The current and voltage values are transmitted at the full 16-bit measured values by default. The IVMON_EN[1:0] bits of register from can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits values across multiple slots. The special 12-bit mode is used when only 24-bit I²S/TDM data can be processed by the host processor. The device should be configured with the voltage-sense slot and current-sense slot off by 1 slot and will consume 3 consecutive 8-bit slots. In this mode the device will transmit the first 12 MSB bits followed by the second 12 MSB bits specified by the preceding slot.

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at the frame boundary.

The time slots for SAR measurements (PVDDL, PVDDH and temperature) are set using SAR_DATA_SLOT[5:0] register bits. To enable sample stream register bit SAR_DATA_TX must be set high. The slot length is selected by bit SAR_DATA_SL of register from .

For TDM final processed audio slot, enable and length settings use AUDIO_SLOT[5:0], AUDIO_TX and AUDIO_SLEN register bits.

Information about status of slots can be find in STATUS_SLOT[5:0] register bits. STATUS_TX register bit set high enables the status transmit.